Speaking at the recent RISC-V Summit Europe 2025 in Paris, Thomas Dombek, head of Digital Integrated Circuits and Systems Department at CEA, looked back on seven years of involvement in the RISC-V ecosystem.
www.eetimes.eu, May. 28, 2025 –
It’s been fifteen years since RISC-V turned the page on closed, proprietary ISAs and opened a new chapter in computing. Its open ISA allows the architecture to be adapted to different application domains, from performance to low-energy consumption and from safety to security. Speaking at the recent RISC-V Summit Europe 2025 in Paris, Thomas Dombek, head of Digital Integrated Circuits and Systems Department at CEA, looked back on seven years of involvement in the RISC-V ecosystem.
“Over the years, we have been at the forefront of heterogeneous integration, always with a close link to semiconductor technology, ultra-low power systems, and efficient AI,” Dombek said. “We have used different types of processing systems, but more and more, research goes around RISC-V processors and surrounding systems.”
Dombek pointed to the INTACT project, launched “over 10 years ago, as soon as the 3D integration technology became available”. INTACT consists of a 96-core architecture composed of six chiplets in FD-SOI [fully depleted silicon-on-insulator] 28-nm technology, which are 3D-stacked onto an active silicon interposer in a 65-nm CMOS process.
“This technology is found today in high-performance systems, but there are still valid challenges for the open hardware community to boost this and get most of the upcoming semiconductor technologies for heterogeneous systems. RISC-V and open hardware seem an obvious choice for us.”
HPDcache, VXP, and VASCO
CEA’s primary concern is system sovereignty and security, which goes hand in hand with other challenges to maintain the efficiency and scalability of solutions. “To do so, we have to build an independent code that is auditable, guarantees interoperability with different elements, and allows system technology co-optimization in the heart of the architecture,” Dombek said. “All these different requirements point to supporting open hardware, in particular RISC-V. Indeed, RISC-V is a flexible standard that allows deep optimization inside the system.”
CEA’s work on RISC-V includes contributions to IP blocks, verification infrastructure, and system codesign efforts. Three examples stood out in Dombek’s presentation.
The first is the High-Performance D-cache (HPDcache), an open-source high-performance, multi-requester, out-of-order L1 data cache for RISC-V cores and accelerators. “The HPDcache delivers a high-throughput, low-latency solution that is compatible with a very flexible workload,” Dombek said. “Technically, from several requesters going into an out-of-order execution with pipeline architecture, you can have multiple outstanding requests without losing performance on the individual cores and coprocessors.”
HPDcache achieves up to 3x performance gains and has become the standard CVA6 cache. Targeting automotive and defense applications, HPDcache is distributed with an industrial-grade verification environment. “It has already been integrated into 32- and 64-bit processor configurations, depending on the type of workload compared to classical cache solutions,” Dombek said. Click here to read more