As semiconductor designs evolve in complexity and scale, the role of interconnect IP becomes increasingly central to performance, power efficiency, and time to market. To address this, Arteris has introduced FlexGen, an AI-augmented network-on-chip (NoC) interconnect IP platform aimed at simplifying and accelerating the design process for system-on-chip (SoC) and chiplet-based architectures.
www.embedded.com, Jun. 03, 2025 –
FlexGen builds on Arteris’s FlexNoC 5 technology and leverages a large library of system IP to automate NoC generation. It is designed to support a broad spectrum of processor architectures, including Arm, RISC-V, and x86. FlexGen integrates machine learning and physical design awareness to optimize topologies based on a user’s performance goals and floor-planning constraints.
The company claims FlexGen can deliver up to a 10× improvement in design productivity, reducing what previously took days or weeks down to just a few hours. Wire length—an important factor in power consumption and signal integrity—can reportedly be reduced by up to 30%. The latency improvements can reach up to 10% depending on the application and topology.
Andy Nightingale, VP of product marketing at Arteris, told Embedded.com that the platform addresses several long-standing pain points in chip design. “We’ve now gone past that point of human capability for efficiently building a right-first-time network-on-chip,” he said. “FlexGen helps automate this process but also allows engineers to retain control where needed.”
The pace of innovation in domains such as automotive autonomy, AI inference, and industrial automation has introduced new pressures on semiconductor teams. Designs now involve significantly more data movement, distributed processing, and architectural heterogeneity—all of which make interconnect planning more challenging.
“Data movement actually accounts for a huge amount of the power draw in a system-on-chip,” Nightingale said. “The overall wire length of the SoC has a big impact on the power of the design. The more efficiently you can move that data, the more power you save, and the cooler the device runs.”
FlexGen was developed in response to these growing challenges. The platform automates the generation of non-coherent NoC topologies, using AI-trained heuristics and physical awareness to balance tradeoffs between power, performance, and area. Instead of requiring manual tuning, FlexGen processes a set of user-defined constraints, such as required bandwidth or latency targets, and then produces an optimized topology.
This approach differs from earlier EDA tools in two significant ways. First, it enables deterministic results—users receive the same output given the same inputs, which is particularly important when working on iterative or derivative designs. Second, it provides incremental flexibility, allowing users to modify constraints or floor plans without restarting the design from scratch.
“You don’t want the design to be completely rewritten; you just want it to change optimally the parts that it needs to change,” Nightingale said.
The platform’s AI system is trained on a dataset of internal and customer designs, which allows it to learn from historical best practices and optimize accordingly. While Arteris did not disclose details of the underlying architecture, the company emphasized that its AI operates on principles different from those of generative large language models.
“What we do is provide a deterministic, repeatable result, which is quite special in the industry,” Nightingale said.
FlexGen is being positioned as a solution not just for increasing productivity but for enabling architectural exploration. With shorter iteration cycles, design teams have more freedom to experiment with alternative topologies and performance constraints, without committing to costly rework.
This has particular value in high-stakes markets such as automotive. An automotive company that develops SoCs for advanced driver-assistance systems implemented FlexGen in its design flow, Nightingale told Embedded.com. According to the company, the ability to generate floorplan-adaptive topologies with complex traffic requirements “within minutes” enabled them to evaluate multiple design paths more quickly than before.
The engineers at the automotive firm previously used Arteris’s FlexNoC product and were experienced with manual configuration workflows. With FlexGen, however, they saw improvements not only in productivity but also in performance characteristics, reporting lower latencies and shorter wire lengths while meeting stringent automotive reliability and power requirements.
For SoC developers working in data center AI, consumer electronics, and 5G, similar benefits are anticipated. Multi-die integration and chiplet-based designs are adding new layers of complexity, and NoC IP must adapt to connect diverse blocks efficiently under tight timing and area budgets. Nightingale said that FlexGen’s ability to account for physical design constraints early in the process gives layout teams a head start, ultimately reducing time spent on timing closure and physical integration.