SAN FRANCISCO, Calif. – Addressing the crowd at EE Times' The Future of Chiplets event at DAC, Arm's Eddie Ramirez called on the industry to adopt robust standards and build a true chiplet marketplace, warning that current semi-custom approaches could limit the economic viability of disaggregated SoCs.
www.eetimes.com, Jun. 27, 2025 –
“We’ve come very far in the last five years,” Ramirez said, noting that most data center SoCs coming out today are chiplet-based, albeit, they are semi-custom designs where a single vendor designs all of the chiplets.
“That model is great, but it’s hard for that model to have a positive [total cost of ownership, TCO] return because what you’ve now done is increase the overall cost of the SoC design,” he said. “You’re paying for multiple chiplets. You’re qualifying multiple chiplets.”
Arm nevertheless sees progress in chiplet reuse, he said. Companies are emerging that specialise in IO chiplets to allow others to focus on compute or accelerator chiplets.
“Where we want to get to as an industry is where there is more of a marketplace, meaning that chiplets are looked on as a product, and by looking at it as a product, you’re looking proactively at how to marry this product to other chiplets in the industry,” he said. “That’s really where the economics and the TCO of chiplet-based designs really starts to make more sense.”
There are three things still needed to make chiplets work, Ramirez said.
“The first thing is making it easy for software developers,” he said. “A lot of us here are more focused on the hardware side of the house, but at the end of the day, deployments will scale if it’s easy for software developers to use.”
Part of what Arm is doing in this area is looking at how to make its compute subsystems work with the whole of the AI stack, which at the basic level means making sure there are standards for how software interacts with hardware, especially chiplet-based hardware.
“We’re also thinking about ways of developing modular firmware,” Ramirez said.
Disaggregated designs add complexity for firmware developers, which Arm is targeting with security, provisioning and telemetry libraries in Kleidi AI. This helps abstract some of the differences in hardware designs, to allow developers to use diverse silicon without having to have a deep understanding of its lower-level properties.
“Today, you can download a Llama3 model, run it on PyTorch, and run it on everything from a cloud instance to a Raspberry Pi, and deploy the same application [across the] variety of silicon without actually having to dive into the details or customize the software for each SoC,” he said.
Secondly, partners from across the supply chain need to come together in a holistic way, he said, in order to enable reusable chiplets from different design points.
Arm’s formalized program for this supply chain is called Arm Total Design. The company is excited to see OEMs joining this ecosystem, Ramirez said.
“We’re starting to see OEMs are starting to spec RFIs and RFQs for the new world of chiplets, meaning that instead of sending a single RFI for a single SoC, they’re actually now using some of the standards work that we’re doing to actually submit RFIs for chiplets themselves,” Ramirez said. “That’s a great sign when we’re seeing the OEMs and the end customer confident that people can deliver chiplet-based designs and that they could actually use multi-vendors for these solutions going forward.”
A group of Arm Total Design ecosystem partners started Project LeapFrog, which Ramirez described as “ambitious.” The aim is to create a large-scale AI platform to compete with Nvidia GPUs in the data center, using chiplets from multiple vendors. The project uses Samsung Foundry’s leading-edge nodes and 3D packaging technologies, compute chiplets from ADTechnology in Korea, and AI accelerator chiplets from Korean startup Rebellions.
“Having companies that can specialize in different areas of the design means that we can now actually start growing the silicon supply base in these different areas, and make it easier for, whether it’s a startup, an ASIC design house, or even a foundry, to be able to compete with some of the larger vendors who are doing chiplet-based designs, but they are doing them all internally,” Ramirez said.
The final piece of the puzzle concerns standards, from UCIe and UA-Link at the physical interface between chiplets, to system standards too.
“[We need to] build fundamental standards so that we remove some of the fragmentation and really unlock the potential of building a lot of different variations of design points using chiplets, but we have to do it in a way that removes that fragmentation,” he said.
Arm has more than 70 partners contributing to its Chiplet System Architecture (CSA) specification, whose first version was released in January.
“We’re looking at ways of how to deploy chiplet-based designs that go beyond just adding UCIE to both chiplets,” Ramirez said.
CSA includes standards for the interfaces required for security and telemetry, for example. It includes different profiles for different types of chiplet-based designs, whether that’s compute to a coherent accelerator, or an IO hub-based design.
“We’d be happy to work with everyone in the industry to really advance some of the underlying standards so that we can get to a point where we have a vibrant chiplet ecosystem and a vibrant marketplace,” Ramirez said.