April 13, 2026 -
In the evolving landscape of chiplet-based system design, efficient and flexible die-to-die connectivity is critical. This AIB C28SOI 10ML Die-to-Die Interface PHY IP core introduces a powerful alternative to closed interconnect ecosystems by combining high performance, low power, and full design transparency.
Built on 28nm FDSOI technology, the PHY implements the AIB 2.0 interface, enabling seamless 32-bit AXI-based communication between dies with deterministic latency and high bandwidth efficiency. Unlike proprietary interconnect solutions, the AIB PHY IP Core is delivered as a white-box implementation with unlimited usage and modification rights, empowering semiconductor companies to tailor the interface to their architecture without licensing constraints or vendor lock-in.
Open Architecture Advantage
While standards such as UCIe aim to unify chiplet ecosystems, they often introduce complex compliance layers, licensing considerations, and integration overhead.
The AIB IP PHY IP Core offers a leaner and more controllable alternative:
Use Cases
The AIB C28SOI PHY IP core redefines die-to-die connectivity by delivering performance comparable to industry standards while preserving full design freedom—making it an ideal choice for companies building differentiated silicon in the chiplet era.
Availability: This AIB PHY IP Core is available for immediate licensing. For more information on licensing options and pricing please drop a request / MailTo
About T2M: T2MIP is the global independent semiconductor technology experts, supplying complex semiconductor IP Cores, Software, KGD and disruptive technologies enabling accelerated development of your Wearables, IOT, Communications, Storage, Servers, Networking, TV, STB and Satellite SoCs.