Company
design-reuse.com
D&R China
Blogs
Industry Articles
D&R Events
IP-SoC Days 2026
IP-SoC Days 2025
IP-SoC Days 2024
IP-SoC Days 2023
IP-SoC Days 2022
IP-SoC 2025
IP-SoC 2024
IP-SoC 2023
IP-SoC 2022
Videos
Subscribe to D&R SoC News Alert
English
Mandarin
Login
Catalog of SIP Cores
System on Chip design resources
Catalog of SIP Cores
System on Chip design resources
Menu
Home
Search IP Core
News
Blogs
Articles
D&R Events
Videos
Subscribe to D&R SoC News Alert
Login
News
Center
Foundation IP
Analog IP
Interface IP
Interconnect IP
Memory Controller & PHY
Peripheral Controller
Wireless IP
Wireline IP
Processor IP
RISC-V
AI Core
Automotive IP
Security IP
IoT
Media IP
Avionics / Space IP
Verification IP
Verification Platform
Design Platform
Asic & IP Design Center
IP-SoC Days
IP-SoC Days 2026
IP-SoC Days 2025
IP-SoC Days 2024
IP-SoC Days 2023
IP-SoC Days 2022
IP-SoC 2025
IP-SoC 2024
IP-SoC 2023
IP-SoC 2022
Industry Articles
Understanding MACsec and Its Integration
(Wednesday, March 26, 2025)
Discover new Tessent UltraSight-V from Siemens EDA, and accelerate your RISC-V development.
(Monday, March 24, 2025)
The Critical Factors of a High-performance Audio Codec - What Chip Designers Need to Know
(Thursday, March 13, 2025)
5 Steps to Confront the Talent Shortage With IP-Centric Design
(Thursday, March 13, 2025)
Density Management in Analog Layout Design: Addressing Issues and Ensuring Consistency
(Monday, March 10, 2025)
Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation
(Monday, March 3, 2025)
How the Ability to Manage Register Specifications Helps You Create More Competitive Products
(Monday, March 3, 2025)
EAVS - Electra IC Advanced Verification Suite for RISC-V Cores
(Monday, February 24, 2025)
Why RISC-V is a viable option for safety-critical applications
(Monday, February 17, 2025)
Dimensioning in 3D space: Object Volumetric Measurement by Leveraging Depth Camera-based Reconstruction on NVIDIA Edge devices
(Monday, February 17, 2025)
What is JESD204B? Quick summary of the standard
(Wednesday, February 12, 2025)
Post-Quantum Cryptography - Securing Semiconductors in a Post-Quantum World
(Monday, February 10, 2025)
Analysis and Summary on Clock Generator Circuits and PLL Design
(Thursday, February 6, 2025)
Understanding why power management IP is so important
(Wednesday, February 5, 2025)
Hardware-Assisted Verification: The Real Story Behind Capacity
(Monday, February 3, 2025)
Bigger Chips, More IPs, and Mounting Challenges in Addressing the Growing Complexity of SoC Design
(Wednesday, January 29, 2025)
SoC design: What's next for NoCs?
(Monday, January 27, 2025)
How to Save Time and Improve Communication Between Semiconductor Design and Verification Engineers
(Monday, January 27, 2025)
Synopsys Foundation IP Enabling Low-Power AI Processors
(Thursday, January 23, 2025)
Accelerating RISC-V development with Tessent UltraSight-V
(Monday, January 20, 2025)
Automotive Ethernet Security Using MACsec
(Monday, January 20, 2025)
What is JESD204C? A quick glance at the standard
(Thursday, January 9, 2025)
Optimizing Power Efficiency in SOC with PVT Sensor-Assisted DVFS Technology
(Monday, January 6, 2025)
Bandgap Reference (BGR) Circuit Design and Transient Analysis in 90nm VLSI Technology
(Monday, January 6, 2025)
Quantum Readiness Considerations for Suppliers and Manufacturers
(Monday, December 16, 2024)
A Rad Hard ASIC Design Approach: Triple Modular Redundancy (TMR)
(Monday, December 16, 2024)
Early Interactive Short Isolation for Faster SoC Verification
(Thursday, December 5, 2024)
Implementing Ultra Low Latency Data Center Services with Programmable Logic
(Tuesday, December 3, 2024)
The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certifiedâ„¢ Level 3 RoT Component Certification
(Monday, December 2, 2024)
Advanced Packaging and Chiplets Can Be for Everyone
(Monday, December 2, 2024)
Timing Optimization Technique Using Useful Skew in 5nm Technology Node
(Monday, November 25, 2024)
Streamlining SoC Design with IDS-Integrateâ„¢
(Wednesday, November 20, 2024)
Last-Time Buy Notifications For Your ASICs? How To Make the Most of It
(Tuesday, November 12, 2024)
CANsec: Security for the Third Generation of the CAN Bus
(Monday, October 28, 2024)
Accelerating SoC Evolution With NoC Innovations Using NoC Tiling for AI and Machine Learning
(Wednesday, October 23, 2024)
How SLEC improves functional verification
(Friday, October 18, 2024)
A new era for embedded memory
(Thursday, October 17, 2024)
Electronic musical instruments design: what's inside counts
(Friday, October 4, 2024)
Casting a wide safety net through post processing Checking
(Monday, September 30, 2024)
Proven solutions for converting a chip specification into RTL and UVM
(Thursday, September 5, 2024)
Revolutionizing Chip Design with AI-Driven EDA
(Monday, September 2, 2024)
An Introduction to Direct RF Sampling in a World Evolving Towards Chiplets - Part 1
(Monday, September 2, 2024)
Optimizing Automated Test Equipment for Quality and Complexity
(Monday, September 2, 2024)
How to cost-efficiently add Ethernet switching to industrial devices
(Wednesday, August 28, 2024)
Optimizing Analog Layouts: Techniques for Effective Layout Matching
(Monday, August 26, 2024)
Why Interlaken is a great choice for architecting chip to chip communications in AI chips
(Wednesday, August 21, 2024)
Fully Automating Chip Design
(Tuesday, August 20, 2024)
Ensure Cybersecurity in the Connected Vehicles Era With ISO/SAE 21434
(Monday, August 19, 2024)
Key considerations and challenges when choosing LDOs
(Monday, August 12, 2024)
Why Transceiver-Rich FPGAs Are Suitable for Vehicle Infotainment System Designs
(Thursday, August 8, 2024)
|
Previous
|
2
|
3
|
4
|
...
|
Next
|
Previous
