Company
design-reuse.com
D&R China
Blogs
Industry Articles
D&R Events
IP-SoC Days 2026
IP-SoC Days 2025
IP-SoC Days 2024
IP-SoC Days 2023
IP-SoC Days 2022
IP-SoC 2025
IP-SoC 2024
IP-SoC 2023
IP-SoC 2022
Videos
Subscribe to D&R SoC News Alert
English
Mandarin
Login
Catalog of SIP Cores
System on Chip design resources
Catalog of SIP Cores
System on Chip design resources
Menu
Home
Search IP Core
News
Blogs
Articles
D&R Events
Videos
Subscribe to D&R SoC News Alert
Login
News
Center
Foundation IP
Analog IP
Interface IP
Interconnect IP
Memory Controller & PHY
Peripheral Controller
Wireless IP
Wireline IP
Processor IP
RISC-V
AI Core
Automotive IP
Security IP
IoT
Media IP
Avionics / Space IP
Verification IP
Verification Platform
Design Platform
Asic & IP Design Center
IP-SoC Days
IP-SoC Days 2026
IP-SoC Days 2025
IP-SoC Days 2024
IP-SoC Days 2023
IP-SoC Days 2022
IP-SoC 2025
IP-SoC 2024
IP-SoC 2023
IP-SoC 2022
Industry Articles
Achieving 200-400GE network buffer speeds with a serial-memory coprocessor architecture
(Monday, October 27, 2014)
Selecting an operating system for an embedded application
(Monday, October 27, 2014)
IC mixed-mode verification: The Sandwiched-SPICE approach
(Monday, October 27, 2014)
Multiple clock domain SoCs: Verification techniques
(Monday, October 27, 2014)
The IoT Spurs the Pursuit of Low Power
(Friday, October 24, 2014)
Rethinking the FFT
(Thursday, October 23, 2014)
Understanding Peak Floating-Point Performance Calculations
(Tuesday, October 21, 2014)
This Isn't Your Father's JTAG Anymore
(Monday, October 20, 2014)
Simplifying SoC Verification by communicating between HVL Env and processor
(Monday, October 20, 2014)
Use test data to diagnose failed memory
(Monday, October 20, 2014)
High-Reliability FPGA Designs
(Thursday, October 16, 2014)
Choosing the right A/D converter architecture and IP to meet the latest high speed wireless standards
(Wednesday, October 15, 2014)
Performance analysis of 8-bit pipelined Asynchronous Processor core
(Monday, October 13, 2014)
Understanding layers in the JESD204B specification: A high speed ADC perspective, Part 2
(Monday, October 13, 2014)
Tampering with the easy targets
(Monday, October 13, 2014)
Security in transit
(Monday, October 13, 2014)
What does 'security' really mean?
(Thursday, October 9, 2014)
Creating, Simulating, and Debugging SVA Code Outside of the Traditional Design/Verification Environment
(Monday, October 6, 2014)
The IoT is turning software development upside down
(Wednesday, October 1, 2014)
Market conditions swing in favor of the custom SoC
(Wednesday, October 1, 2014)
CPU Architects at the Brink: Where to Go Now?
(Monday, September 29, 2014)
Targeting SoC address decoder faults using functional patterns
(Monday, September 29, 2014)
Improve FPGA communications interface clock jitters with external PLLs
(Monday, September 29, 2014)
Understanding layers in the JESD204B specification: A high speed ADC perspective, Part 1
(Thursday, September 25, 2014)
Is FPGA power design ready for concurrent engineering?
(Thursday, September 25, 2014)
Product how-to: Reliable SoC bus architecture improves performance
(Wednesday, September 24, 2014)
Design trade-offs for product development
(Tuesday, September 23, 2014)
RISC-VLIW IP Core for the Airborn Navigation Functional Oriented Processor
(Monday, September 22, 2014)
Addressing MIPI M-PHY connectivity challenges for more efficient testing
(Monday, September 22, 2014)
Low-loss compression of CPRI baseband data
(Friday, September 19, 2014)
Vision in wearable devices: Expanded application and function choices
(Thursday, September 18, 2014)
Building ARM-based Bluetooth-enabled wearables
(Thursday, September 18, 2014)
Reducing Power Consumption while increasing SoC Performance
(Monday, September 15, 2014)
Capturing a UART Design in MyHDL & Testing It in an FPGA
(Thursday, September 11, 2014)
A multitasking kernel in one line of code - almost
(Thursday, September 11, 2014)
What is 802.11ac, anyway?
(Thursday, September 11, 2014)
Testing for Security: Key to Automotive Development
(Thursday, September 11, 2014)
Semiconductor innovations in computer vision and mobile photography
(Monday, September 8, 2014)
An innovative methodology to reduce routing capacitance of ADC channels
(Monday, September 8, 2014)
DO-254 for Dummies: IP & verification process
(Friday, September 5, 2014)
BIST schemes for ADCs
(Wednesday, September 3, 2014)
Bug hunting SoC designs to achieve full functional coverage closure
(Monday, September 1, 2014)
Wearing the Architecture: Evolution in Wearable Electronics
(Monday, September 1, 2014)
Low Power Universal Gates for Approximate Computing
(Monday, September 1, 2014)
A Realtime 1080P30 H.264 Encoder System on a Zynq Device
(Monday, September 1, 2014)
Intelligent Vt structuring to avoid Temperature Inversion for Performance gain
(Monday, September 1, 2014)
Challenges and Benefits of Low Power Design Verification with CPF for a standalone IP
(Monday, September 1, 2014)
Pinning down the acceptable level of jitter for your embedded design
(Thursday, August 28, 2014)
Embedded flash process enhances performance: Product how-to
(Thursday, August 28, 2014)
Using multi-bit flip-flop custom cells to achieve better SoC design efficiency
(Thursday, August 21, 2014)
|
Previous
|
25
|
26
|
27
|
...
|
Next
|
Previous
