Thursday, May 25, 2023

• Generative AI is changing the world - but can it continue to succeed with our current data infrastructure?
• Why we're the GPU of choice for RISC-V
• Designing Smarter Edge AI Devices with the Award-Winning Synopsys ARC NPX6 NPU IP

Wednesday, May 24, 2023

• Update: China may Win in AI Computing
• New Synopsys Report Highlights Key Industry Insights on the Impact of Multi-Die Systems

Tuesday, May 23, 2023

• No one-size-fits-all approach to RISC-V processor optimization
• How does Post-Quantum Cryptography affect the TLS protocol?
• Cadence Welcomes Pulsic, Ltd
• Can the Semiconductor Industry Overcome Thermal Design Challenges in Multi-Die Systems?

Monday, May 22, 2023

• Cadence Collaboration with Kudan and Visionary.ai Enables Rapid Deployment of VSLAM and AI ISP-Based Solutions
• How Vehicle Design Is Influencing Processors
• How Multi-Die Systems Create New Business Opportunities for Semiconductor Companies
• Designing Chips in the Cloud: Four Key Takeaways from SNUG Silicon Valley 2023

Wednesday, May 17, 2023

• Shifting left for success: Highlights from the Siemens EDA User 2 User conference
• How Cloud IC Verification Reduced DRC Runtimes by 65%

Thursday, May 11, 2023

• Expanded access to Arm Virtual Hardware for the entire IoT ecosystem

Wednesday, May 10, 2023

• What Does the Future Hold for AI in Chip Design?

Tuesday, May 9, 2023

• NAND Flash Memory - Key Element For Your Multi-Die Systems Verification - Part 1
• How to Shift Left on Low-Power Design Verification, Early and Quickly

Monday, May 8, 2023

• Pre and Post-Silicon Verification Have Never Been Closer! Leveraging Portable Stimulus for Automatic Test Equipment (ATE)
• Synopsys Acquires Silicon Frontline Technology

Thursday, May 4, 2023

• An Introduction about ATPG in VLSI
• Imparé Imparts Its Insights on Verification in the Cloud

Wednesday, May 3, 2023

• Low-Power IC Design: What Is Required for Verification and Debug?
• How the CXL Standard Improves Latency in High-Performance Computing

Tuesday, May 2, 2023

• RISC-V customization, HW/SW co-optimization, and custom compute
• Moving AMBA forward with multi-chip and CHI C2C
• How Chip Design Was Revolutionized by AI-Enhanced Game Play

Monday, May 1, 2023

• RISC-V customization, HW/SW co-optimization, and custom compute
• CEO Interview: Ravi Thummarukudy of Mobiveil
• How Arm is making it easier to build platforms that support Confidential Computing
• RISC-V's Worldwide Expansion and Andes Technology's Contribution
• The Wonders of Machine Learning: Tackling Lint Debug Quickly with Root-Cause Analysis (Part 3)

Thursday, April 27, 2023

• Arm's prototype chips: What it means for the IC industry?
• Stormy Last Days At Arm Under Softbank Ownership
• Benchmarking Cadence Tools on Arm-based Servers in the Cloud
• Cadence Demonstrates 112G-ELR SerDes IP on TSMC's 3nm Process Technology
• Working with the NimbleAI project to push the boundaries of neuromorphic vision
• Environmental Noise Cancellation (ENC): Part 2 - Noise types and classic methods for Speech Enhancement
• Automotive Battery Management System Using Bluetooth LE

Tuesday, April 25, 2023

• A formal-based approach for efficient RISC-V processor verification

Sunday, April 23, 2023

• Design IP Sales Grew 20.2% in 2022 after 19.4% in 2021 and 16.7% in 2020!

Thursday, April 20, 2023

• Powering the Next Wave of AI Inference with the Rambus GDDR6 PHY at 24 Gb/s
• How Is AI Driving the Next Innovation Wave for Electronic Design?

Tuesday, April 18, 2023

• UFS 4.0 Explained: How the Latest Flash Storage Standard Propels Our 5G World

Monday, April 17, 2023

• 4nm 112G-ELR SerDes PHY IP
• PCIe 6.0 - All you need to know about PCI Express Gen6

Sunday, April 16, 2023

• UFS 4.0 Explained: How the Latest Flash Storage Standard Propels Our 5G World

Friday, April 14, 2023

• Protecting die-2-die interfaces...
• SNUG Silicon Valley 2023: Catalyzing the Future for Our Smart Everything World