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Blogs
Building Verification Infrastructure for Complex PCIe Verification
(Thursday, December 7, 2023)
The Evolution of Generative AI up to the Model-Driven Era
(Thursday, December 7, 2023)
Rambus Expands Quantum Safe Solutions with Quantum Safe Engine IP
(Thursday, December 7, 2023)
Rambus Expands Quantum Safe Solutions with Quantum Safe Engine IP
(Tuesday, December 5, 2023)
Three Smart Steps to Quickly Test a Register Map for Your Entire SoC
(Monday, December 4, 2023)
5G Based LEO satellites will Truly Grow IoT Adoption Worldwide
(Monday, December 4, 2023)
RISC-V to the Core: New Horizons
(Monday, December 4, 2023)
The Ubiquitous USB 2.0: Exploring Its Benefits and Widespread Adoption
(Friday, December 1, 2023)
Customization? Yes! After tape-out? Yes!
(Thursday, November 30, 2023)
Pace of Innovation for Custom Silicon on Arm Continues with AWS Graviton4
(Thursday, November 30, 2023)
Navigating Cache Coherence: The Back-Invalidate Feature in CXL 3.0
(Thursday, November 30, 2023)
Reducing design cycle time for semiconductor startups: The path from MVP to commercial viability
(Wednesday, November 29, 2023)
Unlocking the Power of NAND ONFI Controller IP
(Wednesday, November 29, 2023)
Meet Synopsys.ai Copilot, Industry's First GenAI Capability for Chip Design
(Tuesday, November 28, 2023)
Revolutionize System Verification Flow with a Holistic Approach
(Thursday, November 23, 2023)
Take your neural networks to the next level with Arm's Machine Learning Inference Advisor
(Thursday, November 23, 2023)
Wi-Fi 7 (IEEE 802.11be) & MLO vs. Wi-Fi 6/6E (IEEE 802.11ax): What to Ask for Optimal Design Considerations
(Thursday, November 23, 2023)
Ethernet Encryption: Harnessing the Power of IPSec Shields
(Thursday, November 23, 2023)
Running X-Propagation with Low-Power Simulation
(Thursday, November 23, 2023)
Introducing Cortex-M52: Bringing Arm's AI-optimized Helium architecture to the smallest IoT devices
(Thursday, November 23, 2023)
RISC-V | Solving bus and software deadlock problems in complex SoCs
(Thursday, November 23, 2023)
5 ways to achieve the right level of customization
(Wednesday, November 22, 2023)
How Photonics Can Light the Way for Higher Performing Multi-Die Systems
(Wednesday, November 22, 2023)
Leveraging AI to Optimize the Debug Productivity and Verification Throughput
(Monday, November 20, 2023)
How to Get Started with Model-Based Systems Engineering
(Monday, November 20, 2023)
Unlock the Possibilities with HiFive Unmatched RISC-V Development Boards
(Monday, November 20, 2023)
Synopsys CXL Protocol Verification Solutions Proven with Real World Vendor Devices at the CXL Compliance Test Event
(Friday, November 17, 2023)
Insights Into the Evolutions and Optimizations of PCIe 6.0
(Friday, November 17, 2023)
How Innosilicon makes Fantasy a reality
(Thursday, November 16, 2023)
Synopsys Cloud: The Power of Automated License Management
(Thursday, November 16, 2023)
How Will Angstrom-Scale Chips Advance the Electronics Industry?
(Thursday, November 16, 2023)
Enhance Reliability and Predict Failures in Automotive Electronics
(Thursday, November 16, 2023)
CXL 3.1: What's Next for CXL-based Memory in the Data Center
(Wednesday, November 15, 2023)
The Advancements of DDR5: How it Stacks Up Against DDR4
(Tuesday, November 14, 2023)
Breakthrough in area efficiency of on-chip ESD protection
(Monday, November 13, 2023)
RISC-V Summit US 2023: CHERI in full bloom!
(Friday, November 10, 2023)
UCIe Interoperability Between Intel and Cadence
(Thursday, November 9, 2023)
IMG DXD: A New Horizon for Cloud Gaming
(Wednesday, November 8, 2023)
EDA in the Cloud: Astera Labs, AWS, Arm, and Cadence Report
(Wednesday, November 8, 2023)
Arm-based Cloud Instances Outperform x86 Instances by up to 64% on VP9 Encoding
(Tuesday, November 7, 2023)
NAND vs. NOR Flash Memory: Unpacking the Battle of Non-Volatile Memory
(Tuesday, November 7, 2023)
USB4 Version 2.0 - Link Configurations
(Monday, November 6, 2023)
How Will EDA Benefit from the AI Revolution? - Part 2
(Monday, November 6, 2023)
When Attempts To Establish IP Empires Died
(Monday, November 6, 2023)
Showcasing AI-Driven Analog Design Migration at Samsung SAFE Forum
(Monday, November 6, 2023)
Fine-grained memory protection
(Thursday, November 2, 2023)
Pioneering Seamless Interoperability on Cloud Across the Semiconductor Design Ecosystem
(Thursday, November 2, 2023)
Everything You Need to Know About RISC-V
(Thursday, November 2, 2023)
Debugging RISC-V processors using E-Trace
(Wednesday, November 1, 2023)
Synopsys CXL Protocol Verification Solutions Proven with Real World Vendor Devices at the CXL Compliance Test Event (CTE 002)
(Monday, October 30, 2023)
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