Design & Reuse
AMBA AHB / APB/ AXI (196)
CXL (18)
D2D (58)
Gen-Z (6)
HDMI (82)
I2C (119)
Interlaken (3)
MIL-STD-1553 (3)
MIPI (453)
Multi-Protocol PHY (36)
PCI (248)
RapidIO (6)
SAS (6)
SATA (95)
Smart Card (6)
USB (387)
V-by-One (22)
VESA (71)
Other (63)
248 IP
1
100.0
PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
This Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 5.0 Base Specification with support of PIPE 5.1 interface spec. Lo...
2
100.0
PCIe 6.1 Controller
The Rambus PCI Express® (PCIe®) 6.1 Controller is a configurable and scalable design for ASIC implementations. It is backward compatible to the PCIe 5...
3
100.0
PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency
Multiprotocol low latency, low power SERDES IP....
4
100.0
56G Serdes in 7nm bundled with PCie Gen 5 controller IP
New IP for value conscious designers....
5
100.0
PCIe 7.0 Controller
The Rambus PCI Express® (PCIe®) 7.0 Controller is a configurable and scalable design for ASIC implementations. It is backward compatible to the PCIe 6...
6
100.0
PCIe 7.0 PHY IP supporting the latest features of the evolving PCIe 7.0 specification to enable 128 GT/s and up to x16 lane configurations
The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 7.0 meets today’s demands for higher bandwidth and power efficiency across backplane, and c...
7
100.0
PCIe 7.0 Retimer Controller
The Rambus PCI Express® (PCIe®) 7.0 Retimer Controller provides a complete digital data path solution that delivers best-in-class latency, power and a...
8
100.0
PCIe 6.0 PHY in TSMC (N6, N5, N4P, N3P, N3E)
The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 6.0 meets today’s demands for higher bandwidth and power efficiency across network interfac...
9
100.0
PCIe 6.0 PHY in Samsung (SF5A, SF4X, SF2)
The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 6.0 meets today’s demands for higher bandwidth and power efficiency across network interfac...
10
100.0
PCIe 7.0 PHY in TSMC (N5, N3P, N2P)
The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 7.0 meets today’s demands for higher bandwidth and power efficiency across backplane, and c...
11
100.0
PCIe 7.0 Controller with AXI
The Rambus PCI Express® (PCIe®) 7.0 Controller with AXI is a configurable and scalable design for ASIC implementations. It is backward compatible to P...
12
100.0
PCIe 7.0 Switch
The Rambus PCI Express® (PCIe®) 7.0 Switch is a customizable, multiport embedded switch for PCIe designed for ASIC and FPGA implementations. It enable...
13
85.0
PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
Rambus PCIe 5.0 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 5.0 Controlle...
14
80.0
PCIe 5.0 Customizable Embedded Multi-port Switch
Rambus PCIe 5.0 Multi-port Switch is a customizable, Embedded PCIe Switch designed for ASIC and FPGA implementations enabling the connection of one u...
15
70.0
PCIe Switch for USB4 Hubs, Hosts and Devices
Rambus PCIe Multi-port Switch for USB4 is a customizable, embedded Switch for PCI Express (PCIe) designed for implementations in USB4 devices. A fully...
16
70.0
PCIe Controller Testbench
PCIe Testbench from Rambus emulates a Root Complex device enabling simulation of a PCI Express design. This includes the following features: • R...
17
70.0
PCIe 6.2 Switch
The Rambus PCI Express® (PCIe®) 6.2 Switch is a customizable, multiport embedded switch for PCIe designed for ASIC implementations. It enables the con...
18
50.0
PCIe 4.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
Rambus PCIe 4.0 Controller is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. The Rambus PCIe 4.0 Contr...
19
50.0
PCIe 4.0 PHY in TSMC (28nm, 16nm, 12nm, N7, N3P)
The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...
20
50.0
PCIe 5.0 PHY in TSMC (16nm, 12nm, N7, N6, N5, N4P, N3E, N3P)
The multi-channel Synopsys PHY IP for PCI Express® 5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to meet today’s applicatio...
21
40.0
PCIe Gen6 Controller
Our latest PCIe gen 6 controller IP, which is "NoC aware", provides a high-speed interface for efficient data transfer and system communication, suppo...
22
38.0
PCIe 6.x / PCIe5.x / PCIe4.x / PCIe3.x / PCIe2.x / PCIe1.x Controller
The Controller IP is customer configurable and supports PCIe 6.x/PCIe5.x/PCIe4.x/PCIe3.x/ PCIe2.x/PCIe1.x Specifications. The Controller IP support la...
23
38.0
1 to 64 Gbps PCI-Express (PCIe) 6.0 and CXL 3.0 PHY
The Alphawave PipeCORE PHY IP is a high-performance, low-power, PCIe 1.0 to PCIe 6.0 PHY, that is capable of also operating at 64 Gbps PAM4 PCI Expres...
24
33.0
Ultra Low-Latency IP PCI-express Framework
LeWiz makes available its low-latency PCI-express framework for IP licensing - targeting low-latency applications such as those in the financial secto...
25
30.0
PHY layer solution for PCIe1.1/PCIe2.0 with a serial interface and PIPE3 compliant digital interface
KA13UGPEP20ST001 provides a complete PHY layer solution for PCIe1.1/PCIe2.0 (2.5/5.0Gbps) for single lane application. It has a serial interface and P...
26
25.0
PCIE Gen5 digital controller
Primeexpress PCIE Gen5 digital controller from Primesoc, is well architect,high performance, modular designed and tailor made to plug and play in SOCs...
27
25.0
PCIe Gen5/4 Retimer
Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on each side of the Retime...
28
20.0
PCIe 4.0 PHY in TSMC(6nm,7nm,12nm,16nm)
M31 PCIe 4.0 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. The PCIe 4.0 IP suppo...
29
20.0
PCIe 5.0 PHY IP for Storage and High-Bandwidth Connection
M31 PCIe 5.0 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. The PCIe 5.0 IP suppo...
30
20.0
PCIe 2.0 PHY in GF (40nm, 28nm, 22nm, 12nm)
The multi-channel Synopsys PHY IP for PCI Express® 2.1/1.1 includes Synopsys’ high-speed, high-performance transceiver to meet today’s demands for hig...
31
20.0
PCIe 3.0 PHY in GF (28nm, 22nm)
The multi-channel Synopsys PHY IP for PCI Express® 3.1 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...
32
20.0
Synopsys PCIe 4.0 PHY IP for TSMC N7
The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...
33
20.0
PCIe 4.0 PHY in GF (14nm, 12nm)
The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...
34
20.0
PCIe 2.0 PHY in Fujitsu (40nm)
The multi-channel Synopsys PHY IP for PCI Express® 2.1/1.1 includes Synopsys’ high-speed, high-performance transceiver to meet today’s demands for hig...
35
20.0
PCIe 2.0 PHY in SMIC (40nm, 28nm)
The multi-channel Synopsys PHY IP for PCI Express® 2.1/1.1 includes Synopsys’ high-speed, high-performance transceiver to meet today’s demands for hig...
36
20.0
PCIe 2.0 PHY in TSMC (28nm, 16nm, 12nm)
The multi-channel Synopsys PHY IP for PCI Express® 2.1/1.1 includes Synopsys’ high-speed, high-performance transceiver to meet today’s demands for hig...
37
20.0
PCIe 2.0 PHY in UMC (40nm, 28nm)
The multi-channel Synopsys PHY IP for PCI Express® 2.1/1.1 includes Synopsys’ high-speed, high-performance transceiver to meet today’s demands for hig...
38
20.0
PCIe 3.0 PHY in UMC (28nm)
The multi-channel Synopsys PHY IP for PCI Express® 3.1 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...
39
20.0
PCIe 4.0 PHY in Samsung (14nm, 11nm, SF5A, SF2)
The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...
40
20.0
Pre-verified Interface IP Subsystems reduce design risk and accelerate time-to-market
Customers are increasingly utilizing third-party standards-based IP in their designs, but face several challenges. With more IP and more complex inter...
41
15.0
PCIe 5.0 PHY
With sophisticated architecture and advanced technology, KNiulink SerDes PHY IP with PMA and PCS layer is designed for low power and high performance ...
42
14.0
PCI Express (PCIe) 2.1 Controller
Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe® 2.0 is a solution created for less demanding desi...
43
14.0
PCI Express (PCIe) 5.0 Controller
Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe 5.0 provides the logic required to integrate a roo...
44
14.0
PCI Express (PCIe) 4.0 Controller
Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe 4.0 provides the logic required to integrate a roo...
45
14.0
PCI Express (PCIe) 3.1 Controller
Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe® 3.1 is a solution created for mobile applications...
46
12.0
PCI Express PHY serial link PIPE Transceiver IP cell/hard macro
SMS5000 is a fully integrated CMOS transceiver that handles the full Physical Layer PCI Express protocol and signaling. It contains all necessary AFE ...
47
10.0
PCI Express - Configurable PCI Express 4.0 IP
The Renesas PCIe 4.0 Dual Mode Link Controller IP is compliant with the "PCI Express (PCIe) 4.0 Base Specification". This IP supports the major functi...
48
10.0
PCIe Gen2 PHY
* Endpoint or Root Complex * PIPE includes skip insertion, deletion * PCIe power savings modes * Port bifurcation support...
49
10.0
PCIe 4.0 PHY
With sophisticated architecture and advanced technology, KNiulink SerDes PHY IP with PMA and PCS layer is designed for low power and high performance ...
50
10.0
PCIe 5.0 PHY NCS in TSMC (N7, N6, N5, N3P)
The multi-channel Synopsys PHY IP for PCI Express® 5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to meet today’s applicatio...