Design & Reuse
arrow AMBA AHB / APB/ AXI (192)
arrow CXL (18)
arrow D2D (58)
arrow Gen-Z (6)
arrow HDMI (83)
arrow I2C (98)
arrow Interlaken (2)
arrow MIL-STD-1553 (3)
arrow MIPI (460)
arrow Multi-Protocol PHY (37)
arrow PCI (254)
arrow RapidIO (6)
arrow SAS (6)
arrow SATA (95)
arrow Smart Card (6)
arrow USB (390)
arrow V-by-One (22)
arrow VESA (73)
arrow Other (66)
1875 IP
601
5.0
PDM-to-PCM Conversion with AMBA Interface
The AR36T01 is a soft macro low-power digital microphone interface modulator IP. The IP converts stereo/mono 1-bit pulse-density modulated (PDM) bit s...
602
5.0
Advanced Encryption Standard Module
The CC-AES-APB is a synthesisable Verilog model of a Advanced Encryption Standard module. The AES core can be efficiently implemented on FPGA and ASIC...
603
5.0
General Purpose Input/Output Controller
The CC-GPIO-APB is a synthesisable Verilog model of a General Purpose Input/Output Controller. The GPIO core can be efficiently implemented on FPGA an...
604
5.0
General Purpose Input/Output Controller
The CC-GPIO-AXI is a synthesisable Verilog model of a General Purpose Input/Output Controller. The GPIO core can be efficiently implemented on FPGA an...
605
5.0
SerialLite PHY with PCS
The VSG1G55SL2 is an enhanced High-Speed SerialLite macro with data transfer capabilities of up-to 3.125Gbps. It includes the PCS layer within the Mac...
606
5.0
Peripheral Direct Memory Access Controller
The CC-PDMA-APB-AHB is a synthesisable Verilog model of a peripheral direct memory access controller. The PDMA core can be efficiently implemented on ...
607
5.0
Peripheral Direct Memory Access Controller
The CC-PDMA-AXI-AXI is a synthesisable Verilog model of a peripheral direct memory access controller. The PDMA core can be efficiently implemented on ...
608
5.0
Single Wire Protocol (SWP) Master Analog Front End (AFE) compliant with the ETSI 102.613 standard
The Single Wire Protocol (SWP) Master Analog Front End (AFE) is a fully integrated interface intended to connect the NFC chip (SWP master) to the UICC...
609
5.0
Single Wire Protocol (SWP) Slave Analog Front End (AFE) compliant with the ETSI 102.613 standard
The Single Wire Protocol (SWP) Slave Analog Front End (AFE) is a fully integrated interface intended to connect the UICC (SWP slave) to the NFC chip (...
610
5.0
Single Wire Protocol (SWP) slave digital controller compliant with the ETSI 102.613 standard
The Single Wire Protocol (SWP) Slave Digital Controller is a fully integrated protocol manager intended to interface the UICC (SWP slave) to the NFC c...
611
5.0
MIPI C-PHY/D-PHY Combo CSI-2 TX (Transmitter) IP in TSMC 65LP
The MXL-CPHY-DPHY-CSI-2-TX is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY is configured as a MIPI Master support...
612
5.0
MIPI Compliant D-PHY TSMC 65LP
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...
613
5.0
MIPI CSI-2
The MIPI CSI-2 IP core is a highly scalable and silicon-agnostic implementation of the MIPI Camera Serial Interface 2 version 4.1 targeting ASIC and ...
614
5.0
MIPI D-PHY Universal IP in Samsung 28FDSOI
The MXL-DPHY-UNIV is a high-frequency low-power, low-cost, source-synchronous, physical Layer. The PHY can be configured as a MIPI Master or MIPI Slav...
615
5.0
MIPI I3C Basic Target
The I3C-T core implements a versatile MIPI® Improved Inter Integrated Circuit (I3C) Target controller core suitable for any I3C bus topology & complia...
616
5.0
MIPI SPMI Controller or Target
The SPMI-CTRL core implements a highly featured, easy-to-use controller for the MIPI System Power Management Interface (MIPI-SPMI) bus. It supports th...
617
5.0
MIPI SPMI Host Controller
The System Power Management Interface is a two wire interface that connects the integrated power controller (PC) of a System-on-Chip (SoC) processor s...
618
5.0
MIPI SPMI Target Controller
The System Power Management Interface is a two wire interface that connects the integrated power controller (PC) of a System-on-Chip (SoC) processor s...
619
5.0
MIPI-I3C Combo Host and Target interface controller IP for Sensor and Peripheral connection
The MIPI I3C (Improved Inter Integrated circuit) is a two wire bidirectional Serial Bus for sensor communication. The MIPI I3C interface has been ...
620
5.0
MIPI-I3C Combo IP Host/Target HDR-DDR compliance with Spec v1.1.1
MIPI I3C(Improved Inter Integrated Circuit) is a two-wire bidirectional serial Bus for sensors communication. The MIPI I3C interface has been develope...
621
5.0
SOF-Calibrated 48MHz USB Clock
CT20101 extracts a precise 48MHz clock frequency underlying a USB 1.1 data stream. The device implements a loop that controls the output frequency o...
622
5.0
Configurable System Tick Counter
The CC-SYSTICK-APB is a synthesisable Verilog model of a system tick timer counter controller. The SYSTICK core can be efficiently implemented on FPGA...
623
5.0
Configurable Timer Counter
The CC-TIMER-APB is a synthesisable Verilog model timer counter controller. The TIMER core can be efficiently implemented on FPGA and ASIC technologie...
624
5.0
Configurable Watchdog Timer
The CC-WDT-APB is a synthesisable Verilog model of a watchdog timer controller. The WDT core can be efficiently implemented on FPGA and ASIC technolog...
625
5.0
Low/Full Speed USB Billboard Controller
The CT25100 is a Full-Speed USB controller, which enumerates as Billboard Device. It integrates all necessary infrastructures, including the CT201...
626
5.0
Low/Full Speed USB Physical Layer
CT25201 is a complete and high integrated USB 2.0 low speed and full speed transceiver implementing the physical layer of a USB compliant device. ...
627
5.0
SPI Master / Slave Controller w/FIFO (APB Bus)
The Digital Blocks DB-SPI-MS is a Serial Port Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers. The DB-SPI-MS...
628
5.0
SPI Serial Peripheral Interface Master/Slave
The CC-SPI-APB is a synthesisable Verilog model of a SPI serial peripheral interface Master/Slave controller. The SPI core can be efficiently implemen...
629
5.0
SPI Slave Controller (SPI2APB, SPI2AXI, SPI2AHB Bus)
The Digital Blocks DB-SPI-S-AMBA-BRIDGE is a Serial Port Interface (SPI) Controller Verilog IP Core supporting SPI Slave Interface to APB Master Bus. ...
630
5.0
USB 2.0 Device Controller
...
631
5.0
USB 2.0 Host Controller
...
632
5.0
USB 2.0 Hub Controller
...
633
5.0
USB Power Delivery 3.1 Physical Layer
CT20602 is a complete USB Power Delivery 3.1 Physical Layer. It also implements that part of the USB Power Delivery 3.1 Protocol Layer which are def...
634
5.0
USB-C Interface
CT20601 is a complete USB Type-C Interface which includes optional VCONN and VBUS management features. It implements the dual-role port CC1/CC2 inte...
635
5.0
USB3.2 Device Controller
MosChip USB 3.2 Device Controller softcore semiconductor-IP is designed for USB3.2 SuperSpeedPlus and SuperSpeed USB-Device implementations along with...
636
5.0
USB3.2 Gen2x2 xHCI Host Controller
MosChip USB3.x Host softcore is designed for embedded host applications with USB SSP operations and fall back support of SS and USB2 speed modes over ...
637
5.0
USB3.2 Retimer Controller
MosChip USB3.2 Retimer softcore is designed for use USB Port/Cable Retimer applications with USB SuperSpeedPlus/SuperSpeed link operations The IP has ...
638
5.0
eSPI & SPI Master/Slave Controller w/FIFO (APB, AHB, or AXI Bus)
The Digital Blocks DB-eSPI-SPI-MS-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting the addition of Enhanced SPI (eSPI...
639
5.0
eUSB Repeater
CT20603 IP implements a dual-role capable eUSB2 repeater enabling an eUSB2 PHY in SOCs to support connections with USB2.0 compliant hosts and peripher...
640
4.0556
I3C and I2C Combo
It supports standard I3C, high-speed I3C, and Ultra-higher-speed I3C modes. Push-pull operation in I3C modes. Supports I2C standard mode, fast mode, f...
641
4.0556
Open-drain I2C and SMBUS, DDC, CEC & HPD IO offerings
Certus is pleased to offer I2C open-drain IOs across multiple process technologies. The Certus I2C IO can support external supplies of 1.8V, 3.3V and...
642
4.0
I2C Controller (AMBA APB <-> I2C)
The I2C Controller provides access to devices with I2C interface. It accepts the Read / Write commands from APB and converts it to the serial I2C acce...
643
4.0
I2C Master Controller
The ntI2C_M is an I2C-bus multi-master interface controller and provides a cost-effective solution for a wide range of applications that require a low...
644
4.0
SAS 1-to-1 Speed Bridge with Sandbox
The IntelliProp SAS Bridge with Sandbox (IPP-SS115A-BR) design provides SAS compliant connections to a SAS host and a SAS device. The host and device ...
645
4.0
SAS Initiator Core
The IntelliProp IPC-SS105A-HI SAS Initiator Core is an industry standard Serial-SCSI (SAS) initiator core that enables host designs to connect to high...
646
4.0
SAS Target Core
The IntelliProp IPC-SS107A-DT SAS Target Core is an industry standard Serial-SCSI (SAS) Core that enables device applications to connect to high throu...
647
4.0
SATA "Y" Bridge
The IntelliProp SATA "Y" Bridge design (IPP-SA111A-BR) provides SATA compliant connections per SATA-IO 3.3 and a standard SATA interface to access dri...
648
4.0
SATA "Y" RAID Bridge without NCQ
The IntelliProp IPP-SA112A-BR SATA “Y” Bridge with RAID design provides SATA compliant connections and a standard SATA interface that performs RAID0 t...
649
4.0
SATA 1-to-1 Speed Bridge with Sandbox
The IntelliProp SATA 1-to-1 Speed Bridge with Sandbox (IPP-SA110A-BR) design provides SATA compliant connections to a SATA host and a SATA device. The...
650
4.0
SATA Bridge Platform (Optional: AES, Hardware Datapath)
The IntelliProp SATA Bridge Platform is an extensible IP Core which encompasses a SATA Device core, a SATA Host core, along with an embedded processor...