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1866 IP
1201
0.0
V-by-One/LVDS Tx IP, Silicon Proven in GF 22FDX
Based on internal equipment connections, the V-by-One® HS technology aims to transmit video signals at high data rates. The requirements to build a tr...
1202
0.0
6.25G SerDes in 55nm
The Actt's 6.25G SerDes IP is a 4-Channel Serdes configuration with 1 PLL, 4 TX channels and 4 RX channels. It’s based on SMIC 55nm embedded-flash tec...
1203
0.0
2.5G MIPI D-PHY in HLMC 28nm
The ACTT family of interface IP for MIPI protocols is leading the way with mobile-optimized low power and high performance. Compliant with the specifi...
1204
0.0
1.5G MIPI D-PHY in SMIC 130nm~28nm
The ACTT family of interface IP for MIPI protocols is leading the way with mobile-optimized low power and high performance. Compliant with the specifi...
1205
0.0
2.5G MIPI D-PHY in TSMC 22nm
The ACTT family of interface IP for MIPI protocols is leading the way with mobile-optimized low power and high performance. Compliant with the specifi...
1206
0.0
4.5Gbps/lane MIPI D-PHY in SMIC 28HKC+
BriteSemi’s MIPI D-PHY supports speed up to 4.5Gbps per lane and an aggregate data rate of 18Gbps, which can provide high-performance MIPI D-PHY solut...
1207
0.0
2.5Gbps/lane MIPI D-PHY in SMIC 40NLL
BriteSemi’s MIPI D-PHY supports speed up to 4.5Gbps per lane and an aggregate data rate of 18Gbps, which can provide high-performance MIPI D-PHY solut...
1208
0.0
I/O LIbrary
Specialty I/O solutions - Higher voltage tolerance - higher ESD robustness - Configurable...
1209
0.0
30G MR Multi-Protocol SerDes (MPS) PHY
Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challengings applications The ...
1210
0.0
40G Ultralink D2D PHY for TSMC N3P
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
1211
0.0
40G Ultralink D2D PHY for TSMC N5P
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
1212
0.0
40G Ultralink D2D PHY for TSMC N6, N7
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
1213
0.0
112G PHY in TSMC (N7, N5)
Synopsys IP Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and high perfor...
1214
0.0
112G VSR PHY in TSMC (N5, N3P)
Synopsys IP Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and high perfor...
1215
0.0
112G-ULR PAM4 SerDes PHY for Samsung SF5A
112G-ULR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channel The Cadence 112Gbps ...
1216
0.0
112G-ULR PAM4 SerDes PHY for TSMC N3E/N3P
112G-ULR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channel The Cadence 112Gbps ...
1217
0.0
112G-ULR PAM4 SerDes PHY for TSMC N5/N4P
112G-ULR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channel The Cadence 112Gbps ...
1218
0.0
112G-ULR PAM4 SerDes PHY for TSMC N6/N7
112G-ULR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channel The Cadence 112Gbps ...
1219
0.0
112G-VSR for Rapidus 2nm
112G-VSR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channel The Cadence 112Gbps ...
1220
0.0
112G-VSR for TSMC N3E/N3P
112G-VSR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channel The Cadence 112Gbps ...
1221
0.0
32-bit, 33 MHz Multifunction Target Interface
The PCI-T32MF implements a target-only PCI interface compliant with the PCI 2.3 specification. It supports a 32-bit address/data bus and operates up t...
1222
0.0
32-bit, 33 MHz PCI Target Interface Core
The main PCI-T32 Interface core purpose is to isolate the user from having to solve complex problems of the PCI interface implementation and let the u...
1223
0.0
32-bit/33,66Mhz PCI Host Bridge
...
1224
0.0
12.5G Multiprotocol Serdes IP, Silicon Proven in SMIC 12SF++
The multi-protocol SerDes PHY includes Peripheral Component Interconnect Express (PCIe) conforming with PCIe 2.0 Base Specification with support for P...
1225
0.0
12.5G Multiprotocol Serdes IP, Silicon Proven in SMIC 40LL
The multi-protocol SerDes PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 2.0 Base Specification with support of P...
1226
0.0
12.5G Multiprotocol Serdes IP, Silicon Proven in TSMC 28HPC+
The multi-protocol SerDes PHY consists of Serial ATA (SATA) conforming with SATA 3.0 Specification, Peripheral Component Interconnect Express (PCIe) c...
1227
0.0
12.5G Multiprotocol Serdes IP, Silicon Proven in UMC 28HPC
The multi-protocol SerDes PHY consists of Serial ATA (SATA) conforming with SATA 3.0 Specification, Peripheral Component Interconnect Express (PCIe) c...
1228
0.0
12.5G Serdes in SMIC 40NLL
Brite Semiconductor‘s Serdes provides 2.5-32Gbps multi-rate SERDES IP which is designed for smooth integration of Multiple SERDES lanes demonstrate go...
1229
0.0
224G Ethernet PHY in Samsung (SF4X)
The Synopsys 224G Ethernet PHY IP, an integral part of Synopsys’ high-speed SerDes IP portfolio, meets the growing high bandwidth and low latency need...
1230
0.0
224G Ethernet PHY IP for TSMC N3P
The Synopsys 224G Ethernet PHY IP, an integral part of Synopsys’ high-speed SerDes IP portfolio, meets the growing high bandwidth and low latency need...
1231
0.0
224G-LR SerDes PHY for Rapidus 2nm
224G-LR SerDes PHY enables 1.6T and 800G networks The Cadence 224G SerDes PHY for UALink enables the emerging 1.6T and 800G scale-up networks for hyp...
1232
0.0
224G-LR SerDes PHY for TSMC N3E/N3P
224G-LR SerDes PHY enables 1.6T and 800G networks The Cadence 224G SerDes PHY for UALink enables the emerging 1.6T and 800G scale-up networks for hyp...
1233
0.0
224G-LR SerDes PHY for UALink for Intel 18A
224G-LR SerDes PHY enables 1.6T and 800G networks for UALink The Cadence 224G SerDes PHY for UALink enables the emerging 1.6T and 800G scale-up net...
1234
0.0
224G-LR SerDes PHY for UALink for TSMC N3E/N3P
224G-LR SerDes PHY enables 1.6T and 800G networks for UALink The Cadence 224G SerDes PHY for UALink enables the emerging 1.6T and 800G scale-up netwo...
1235
0.0
128 Channel Analog Front-End
PMCC_XCM_64X64_A IP block is a 128 channels analog front-end. The IP block consists of 128 variable gain amplifiers (VGAs), 128 2-bit digitizers, bias...
1236
0.0
I2C Bus Master / Slave Controller Interface with FIFO
The I2C is a two-wire, bi-directional serial bus, which provides a simple and efficient method of short distance data transmission between many device...
1237
0.0
I2C Bus Master Controller Core
The I2C-MS core is a controller for the Inter-Integrated Circuit (I2C) bus. The highly configurable core can implement an I2C bus master, slave, or a ...
1238
0.0
I2C Host / Device Bus Controller
The synchronous I2C interface is a block that interconnects an APB bus. The APB - I2C Bridge interfaces to the APB bus on the system side and the I2C ...
1239
0.0
I2C Master / Slave Controller with FIFO (AXI & AXI-Lite Bus)
The I2C is a two-wire, bi-directional serial bus, which provides a simple and efficient method of short distance data transmission between many device...
1240
0.0
I2C Master Controller w/FIFO (AHB & AHB-Lite Bus)
The Digital Blocks DB-I2C-M-AHB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC, or other high performance microprocessor via the AMBA 2.0 AP...
1241
0.0
I2C Master Controller w/FIFO (AXI & AXI-Lite Bus)
The Digital Blocks DB-I2C-M-AXI Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC, or other high performance microprocessor via the AMBA 2.0 AX...
1242
0.0
I2C Master IP
I2C Master interface provides full support for the two-wire I2C synchronous serial interface, compatible with I2C version 6.0 specification. Through i...
1243
0.0
I2C Slave Controller - Low Power, Low Noise Config with APB Interface
The Digital Blocks DB-I2C-S-SCL-CLK-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA...
1244
0.0
I2C Slave Controller w/FIFO (AHB Bus)
The Digital Blocks DB-I2C-S-AHB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 2.0/3.0...
1245
0.0
I2C Slave Controller w/FIFO (APB Bus)
The Digital Blocks DB-I2C-S-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 2.0 APB...
1246
0.0
I2C Slave Controller w/FIFO (AXI Bus)
The Digital Blocks DB-I2C-S-AXI Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 4/3 AXI...
1247
0.0
I2C Slave Controller with User Register Array / Memory / FIFO / AMBA Interface
The DB-I2C-S-REG is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs interfacing to user registers while autonomous i...
1248
0.0
I2C Slave IP
I2C Slave interface provides full support for the two-wire I2C synchronous serial interface, compatible with I2C version 6.0 specification. Through it...
1249
0.0
I2C Slave To AHB Bridge IP
I2C Slave To AHB Bridge interface provides full support for the two-wire I2C synchronous serial interface, compatible with I2C version 6.0 specificati...
1250
0.0
I2C Slave To AXI Bridge IP
I2C Slave To AXI Bridge interface provides full support for the two-wire I2C synchronous serial interface, compatible with I2C version 6.0 specificati...