Design & Reuse
Catalog of SIP Cores
System on Chip design resources
arrow AMBA AHB / APB/ AXI (197)
arrow CXL (21)
arrow D2D (1)
arrow Gen-Z (6)
arrow HDMI (88)
arrow I2C (96)
arrow Interlaken (3)
arrow MIL-STD-1553 (3)
arrow MIPI (498)
arrow Multi-Protocol PHY (33)
arrow PCI (227)
arrow RapidIO (6)
arrow SAS (5)
arrow SATA (74)
arrow Serdes (94)
arrow Smart Card (3)
arrow USB (398)
arrow V-by-One (22)
arrow VESA (80)
arrow Other (35)
1890 IP
1351
0.0
UFS 5.0 Host Controller compatible with M-PHY 6.0 and UniPro 3.0
Universal Flash Storage (UFS) is a JEDEC standard for high performance mobile storage devices suitable for next generation data storage. UFS is also a...
1352
0.0
UFS Device IP
The SmartDV UFS DEVICE IP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The UFS...
1353
0.0
8G Multiprotocol Serdes IP, Silicon Proven in SMIC 14SF+
High performance SERDES IP designed for chips that perform high bandwidth data communication while operating at low power consumption....
1354
0.0
IGASERT08A, Derivative IP of IGPSERT12A Lane-based 1 - 12.5 Gbps Enterprise Multi-Standard SerDes
The GUC's EMS-PHY SerDes supports multiple high speed wire-line communication standards. Supported standards include 1GE, XAUI, RXAUI, XFI, 10GBase-KR...
1355
0.0
RGB to CCIR 601 / 656 Encoder
The Digital Blocks DB1892AXI RGB to CCIR 601 / CCIR 656 Encoder interfaces RGB data along with synchronization signals from a LCD Controller such as D...
1356
0.0
SGMII PHY
The Innosilicon SGMII PHY is a highly programmable module that processes high-speed serial data to parallel data compatible with the IEEE802.3 1000BAS...
1357
0.0
FH-OFDM Modem
...
1358
0.0
AHB / AXI4 - Lite to AXI4-Stream Bridge
The MM2ST IP core bridges the streaming interfaces of a peripheral or accelerator to a memory-mapped AMBA® AHB or AXI4-Lite bus. Designed for ease ...
1359
0.0
AHB 4 Channel DMA Controller
The DMA is a multiple-channel direct memory access controller. The DMA IP Core is a Verilog HDL design that can be used in ASIC, Structured ASIC and F...
1360
0.0
AHB AES with DMA
The Advanced Encryption Standard (AES) IP Core is a complete hardware implementation encryption/decryption algorithm described in the U.S. Government ...
1361
0.0
AHB Arbiter IP
SmartDV's AHB Arbiter IP is a silicon-proven solution that efficiently manages multiple AHB master interfaces competing for bus access in AMBA® AHB-ba...
1362
0.0
AHB Channel with Decoder and Data Mux
The AHB Channel provides the necessary infrastructure to connect as many as 7 AHB Slaves (numbered 1-7) to an AHB bus Master. The AHB Channel perform...
1363
0.0
AHB Compliant Nand Flash Controller
NAND Flash Controller has a built-in AHB Slave Interface, handles all sorts of Nand Flash commands, address & data sequences. It allows the users to a...
1364
0.0
AHB Decoder IP
SmartDV’s AHB Decoder IP core is a silicon-proven solution designed to simplify address decoding and routing within AMBA-based SoC architectures. It e...
1365
0.0
AHB External Bus Interface
The AHB External Bus Interface (EBI) allows a CPU or AHB Master (such as a DMA core) to transmit and receive data to an external device such as an ext...
1366
0.0
AHB Lite to AXI Bridge
The AHB Lite to AXI Bridge translates an AHB Lite bus transaction (read or write) to an AXI bus transaction. It is expected that the AXI clock and the...
1367
0.0
AHB Low Power Subsystem - ARM Cortex M0
The AHB Low Power Subsystem is an AMBA® based system that is useful as the basic digital infrastructure for building low power SOCs. The subsystem co...
1368
0.0
AHB Multilayer Interconnect
The AHB-MLIC is a multi-layer AMBA® AHB bus fabric connecting an arbitrary number of bus masters to an arbitrary number of slaves. The multilayer fa...
1369
0.0
AHB Multilayer Interconnect IP
SmartDV’s AHB Multilayer Interconnect IP is a silicon-proven, high-throughput solution designed to manage complex on-chip communication in SoC designs...
1370
0.0
AHB Performance Subsystem - ARM Cortex M0
The AHB Performance Subsystem is an AMBA® based system that is useful as the digital infrastructure for building low power SOCs needing additional per...
1371
0.0
AHB Performance Subsystem - ARM Cortex M3
The AHB Performance Subsystem is an AMBA® based system that is useful as the digital infrastructure for building low power SOCs needing additional per...
1372
0.0
AHB Secure Subsystem - ARM Cortex M3
The Silvaco Secure AHB Performance Subsystem is a high-performance AHB subsystem that allows for a high level of hardware and software security. It in...
1373
0.0
AHB Single Channel DMA Controller
The DMA is a configurable single channel direct memory access controller. The DMA IP Core is a Verilog HDL design that can be used in ASIC, Structured...
1374
0.0
AHB Slave to SPI Master
The AHB-Lite to SPI Bridge is used to translate 32-bit AHB-Lite Writes and Reads to Writes and Reads over a SPI interface. A custom 32-bit protocol i...
1375
0.0
AHB Subsystem
The AHB-SBS is an integrated, verified, AMBA® 3.0 interconnect and peripherals subsystem ready for embedded applications using processors with AHB bus...
1376
0.0
AHB to APB Bridge
The AHB to APB bridge is an AHB slave, providing an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are...
1377
0.0
AHB To APB Bridge IP
SmartDV’s AHB to APB Bridge IP is a high-performance solution that enables seamless communication between the high-speed AMBA AHB bus and the low-powe...
1378
0.0
AHB to APB Bus Bridge
The AHB to APB Bridge translates an AHB bus transaction (read or write) to an APB bus transaction. This is accomplished via two small state machines ...
1379
0.0
AHB to AXI Bridge IP
SmartDV’s AHB to AXI Bridge IP Core provides a seamless interface between AMBA AHB and AXI protocols, enabling smooth integration of legacy AHB-based ...
1380
0.0
AHB to Parallel Bridge for Audio CODEC
dos_AHB_parallel_bridge is a Parallel interface for Codec connection. Support for multiple channels. Each channel includes a FIFO accessible from para...
1381
0.0
AHB-Lite to AHB-Lite Asynchronous Bridge
The AHB-Lite to AHB-Lite Asynchronous Bridge translates an AHB-Lite bus transaction (read or write) on one clock domain to an AHB-Lite bus transacti...
1382
0.0
CHI to UCIe Bridge IP
SmartDV’s CHI to UCIe Bridge IP enables seamless protocol translation between Arm’s Coherent Hub Interface (CHI) and the Universal Chiplet Interconnec...
1383
0.0
PHY for PCIe 5.0 and CXL for TSMC
Cadence 32G NRZ multi-protocol PHY The Cadence® 32/25Gbps Multi-Link and Multi-Protocol PHY IP for TSMC is a high-performance SerDes operating from 1...
1384
0.0
PHY for PCIe 6.0 and CXL for Samsung
Most advanced PHY and Controller for HPC, AI/ML, Data communications, networking, and storage systems The Cadence® PHY IP for PCI Express® (PCIe®) 6....
1385
0.0
PHY for PCIe 6.0 and CXL for TSMC N4P/N5P
Most advanced PHY and Controller for HPC, AI/ML, Data communications, networking, and storage systems The Cadence® PHY IP for PCI Express® (PCIe®) 6....
1386
0.0
PHY for PCIe 7.0 and CXL for TSMC N3E/N3P
Most advanced PHY and Controller for HPC, AI/ML, Data communications, networking, and storage systems The Cadence® PHY IP for PCI Express® (PCIe®) 7....
1387
0.0
PHY IP for PCIe 6.0 on TSMC N5
The multi-channel Synopsys PHY IP for PCI Express (PCIe) 6.0 meets today’s demands for higher bandwidth and power efficiency across network interface ...
1388
0.0
PHY layer solution for PCIe1.1/PCIe2.0 with a serial interface and PIPE3 compliant digital interface
KA13UGPEP20ST001 provides a complete PHY layer solution for PCIe1.1/PCIe2.0 (2.5/5.0Gbps) for single lane application. It has a serial interface and P...
1389
0.0
Bi-directional AMBA AHB/AHB bridge
The bi-directional AHB/AHB Bridge is used to interconnect high-speed and low-speed AMBA AHB buses. The bridge supports synchronous clocks with any fre...
1390
0.0
Video-by-One Receiver IP_16ch
This document introduces the low power Innosilicon Video-by-One (VBO) Receiver IP containing PHY and controller. Innosilicon VBO RX is designed for re...
1391
0.0
Video-by-One Transmitter IP_8ch
Innosilicon VBO TX IP is designed for transmitting video data from a video source device to a display device. It is compatible with V-By-One HS 1.4 st...
1392
0.0
High Performance Second Generation Extended MIPI CSI2 Receiver
Latest and forthcoming CMOS image sensors surpass 10M pixels, and output video at 30 and even 60 fps. This development requires high bandwidth betwe...
1393
0.0
High Speed Access & Test IP PCIE Version
High speed access for test and in-chip sensor & monitor data throughout the silicon lifecycle. Within the SiliconMAX Platform, High-Speed Access & Tes...
1394
0.0
High Speed Access & Test IP USB Version
High speed access for test and in-chip sensor & monitor data throughout the silicon lifecycle. Within the SiliconMAX Platform, High-Speed Access & Tes...
1395
0.0
Highly configurable high-speed serial link controller
The GRHSSL IP is a highly configurable high-speed serial link controller, described in VHDL. It can implement: * SpaceFibre controller (GRSPFI) * W...
1396
0.0
Highly configurable Interlaken ILA & ILK
Tamba Networks offers a highly configurable Interlaken ILA and ILK core. The core is compliant with the Interlaken and Interlaken look-aside specifica...
1397
0.0
Digital FIR filter with APB interface
The eSi-FIR core provides an interface to filter and decimate time interleaved multi-channel data....
1398
0.0
Digital IIR filter with APB interface
A range of 5th to 11th order digital IIR filters for conditioning and optionally decimating data from an external source and to DMA the output into pr...
1399
0.0
MIL STD 1553 Controller IP
SmartDV’s MIL-STD-1553 Controller IP is a silicon-proven solution designed to meet the stringent reliability and interoperability requirements of mili...
1400
0.0
Mil-Std-1553B/AS15531 Interface
The GR1553B core implements the MIL-STD-1553B (Notice 2) data bus protocol, with ability to serve as Bus Controller (BC), Remote Terminal (RT) or Bus ...