251 1.0

DVB-S2X LDPC/BCH Decoder DVB-S2X is the next generation satellite transmission standard that extends its well-established predecessor DVB-S2. The new specification allows for ...

252 1.0

DVB-S2X Demodulator The Creonic DVB-S2X demodulator is a low-complexity high-performance solution that allows for symbol rates of up to 100 MSymb/s on state-of-the-art FP...

253 1.0

DVB-S2X Modulator The Creonic DVB-S2X high performance modulator performs all tasks of an inner transmitter. The modulator expects BBFrames after mode adaptati...

254 1.0

DVB-S2X Wideband Demodulator The Creonic DVB-S2X high performance wideband demodulator performs all tasks of an inner receiver and achieves throughputs of up to 500 ...

255 1.0

DVB-S2X Wideband Modulator The Creonic DVB-S2X high performance wideband modulator performs all tasks of an inner transmitter. The modulator expects BBFrames after mode adaptati...

256 1.0

DVB-S2X Wideband LDPC/ BCH Decoder The Creonic DVB-S2X wideband decoder is a scalable solution that allows for symbol rates of up to 500 MSymb/s on state-of-the-art FPGAs...

257 1.0

5G-NR LDPC Decoder 5G NR is the mobile broadband standard of the 5th generation. A new rate compatible structure for LDPC codes are employed for channel coding to fulfil...

258 1.0

CCSDS SCCC Turbo Encoder and Decoder The recommended CCSDS 131.2-B-1 standard introduces a Serial Concatenated Convolutional Code (SCCC). Main goal of this code is to allow an efficient u...

259 1.0

CCSDS 231.0 LDPC Encoder and Decoder The CCSDS 231.0 LDPC IP supports the LDPC coding schemes as defined by the CCSDS standard. The LDPC codes with rate 1/2, coded block lengths 128 and 5...

260 1.0

DVB-RCS2 Multi-Carrier Receiver DVB-RCS2 (Digital Video Broadcast – Second Generation DVB Interactive Satellite System) is the latest ETSI standard of the second generation for digit...

261 1.0

XAUI PHY The Innosilicon XAUI PHY is a highly programmable module that processes high-speed serial data to parallel data compatible with the IEEE802.3 standard...

262 1.0

Synchronous Ethernet (SyncE) ESMC and Enhanced ESMC core NetTimeLogic’s Synchronous Ethernet (SyncE) Node is a full hardware (FPGA) only implementation of an ESMC frame Handler and State selector. The whole ...

263 1.0

SPI Master Serial Interface Controller Master serial interface compatible with the popular SPI standard. Features a simple command interface and permits multiple SPI slaves to be controll...

264 1.0

SPI Slave Serial Interface Controller Slave serial interface compatible with the popular SPI standard. Permits an SPI Master to communicate with your FPGA, CPLD or ASIC device. The contr...

265 1.0

Packet-based Digital Radio Link Fully custom Digital Radio Link based on either our FSK or PSK modulation schemes. Data is split into packets or frames and modulated for transmissio...

266 1.0

LDPC Decoder for DVB-S2 ...

267 1.0

HomePlug Turbo Decoder On the transmitter side, the PHY layer receives its inputs from the Media Access Control (MAC) layer. There are three separate processing chains: A) H...

268 1.0

Non-binary LDPC Decoder A powerful Forward Error Correction (FEC) subsystem is needed in almost all wireless communication systems. Low-Density Parity-Check (LDPC) codes are ...

269 1.0

AR4JA LDPC Decoder AR4JA LDPC decoder is a configurable design that allows runtime configuration for decoding different code rates (i.e., 1/2, 2/3 and 3/4). To obtain hi...

270 1.0

LDPC Decoder for 802.11 This is an LDPC decoder compliant with the IEEE 802.11 n/ac/ax standards. It supports high throughput,...

271 1.0

CCSDS 131.2 Wideband Modulator The Creonic CCSDS high performance modulator performs all tasks of an inner transmitter. The modulator expects SCCC (Serial Concatenated Convolutional...

272 1.0

DVB-S2X Multi-Carrier Demodulator The Creonic DVB-S2X high performance multi-carrier demodulator performs all tasks of an inner receiver while processing up to 36 carriers in parallel....

273 1.0

GPON FEC 2.5 Gbps This high performance core is a full featured Forward Error Correction encoder and decoder, specially designed for high speed optical networks or any ...

274 1.0

UDP/IP Hardware Protocol Stack Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone o...

275 1.0

High Throughput QAM Demapper This is a high throughput QAM constellation demapper and Log Likelihood Ratio (LLR) bit-metric generator. The core is capable of accepting a new equa...

276 1.0

High Throughput Reed Solomon Decoder This is a Reed Solomon decoder capable of operating with shortened codewords. The basic mother rate is (N,K) = (255,239) which has 16 parity bytes an...

277 1.0

Medium throughput, compact Reed Solomon decoder This implementation of a M=8 Reed Solomon decoder has been designed to use a minimum set of resources whilst maintaining a medium throughput and flexi...

278 1.0

High-throughput Low-memory Viterbi Decoder This IP core is available in either normal or high throughput configurations. The normal configuration instances a single fully parallel stage, equiva...

279 1.0

Ultra Low-power, compact Hybrid Viterbi Decoder This IP core is available with a configurable number of ACS units to suit a range of throughput requirements. The default configuration instances 4 AC...

280 1.0

Industry reference DVB-RCS turbo decoder TC1000 implements the turbo code specified by DVB-RCS for Interactive 2-way satellite systems. This turbo code used offers a very high flexibility in ...

281 1.0

High-Speed Turbo Product Code decoder TC3404 is a 2D TPC decoder that is optimised for high-speed. A single Core achieves in excess of 200 Mbps user rate with the latest FPGA families (Str...

282 1.0

CCSDS turbo decoder TC6000 is a CCSDS turbo decoder....

283 1.0

China Multimedia Mobile Broadcasting (CMMB) LDPC decoder TC4300 is a LDPC decoder designed for China Multimedia Mobile Broadcasting (CMMB) specifications. The Core is a stand-alone module, with no external m...

284 1.0

LTE / HSPA turbo decoder TC1700 is a FEC receiver adressing LTE, LTE-A, WiMAX, HSPA/+, and legacy 3G standard. It cover Rate matching , HARQ combining and turbo decoding. The...

285 1.0

ITU-Ghn LDPC Encoder / Decoder TC4400 is a LDPC decoder core that is fully compliant with ITU G.hn (wireline home networking) specifications. It support a decoded throughput up to 1...

286 1.0

Gigabit Ethernet MAC with AVB The Arasan Gigabit Ethernet Media Access Controller IP is compliant with the Ethernet IEEE 802.3-2008 standard. In addition, the Gigabit Ethernet MAC...

287 1.0

High Performance Turbo Code TC1600 is ideally suited for applications requiring small to medium block sizes in order to reduce latency and offer a high physical layer flexibility...

288 1.0

Gigabit-range, low complexity LDPC decoder TC4902 is ideally suited for applications requiring a very efficient throughput/area ratio, while not sacrificing SNR performance. TC4902 implements a...

289 1.0

DVB-RCS2 turbo decoder TC1620 is a high performance turbo decdoer Core compliant with DVB-RCS2 specifications. Ideally suited fo systems requiring flexibility, short/medium ...

290 1.0

Flexible LDPC encoder/decoder TC5100 is a highly flexible LDPC encoder/decoder Core. It can essentially cover all possible quasi-cyclic LDPC codes: WiFi, WiMAX, proprietary codes, ...

291 1.0

LTE / WiFi Viterbi decoder TC1720 is a high throughput and low latency Viterbi decoder optimized for WiFi and LTE applications. It covers optionally also WCDMA specifications....

292 1.0

10G/25G UDP/IP Hardware Protocol Stack Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone o...

293 0.3729

A bridge to convert the slave SPI interface to the master I2C interface and vice versa The dti_spi_to_i2c is a bridge to convert the slave SPI interface to the master I2C interface and vice versa....

294 0.3729

A bridge to convert the slave SPI interface to the master UART interface and vice versa The dti_spi_to_uart is a bridge to convert the slave SPI interface to the master UART interface and vice versa....

295 0.118

10/100 Ethernet PHY IP, UMC 90nm SP process 10/100 Base-TX Fast Ethernet PHY, UMC 90nm SP/RVT Low-K Logic process....

296 0.118

10/100 Ethernet PHY IP, UMC 0.13um HS/FSG process 10/100 Base-TX Fast Ethernet PHY, UMC 0.13um HS/FSG Logic process....

297 0.118

10/100 Ethernet PHY IP, UMC 0.18um MS process 10/100 Base-TX Fast Ethernet PHY, UMC 0.18um MMC process....

298 0.118

10BASE-T/100BASE-TX/100BASE-FX Energy Efficient Ethernet PHY; UMC 28nm HPC/Low-K process 10BASE-T/100BASE-TX/100BASE-FX Energy Efficient Ethernet PHY; UMC 28nm HPC/Low-K process...

299 0.118

0.13um DSP Based Fast Ethernet PHY, based on FXEDP110HC0A HJ026a and add 100BASE-FX feature. 0.13um DSP Based Fast Ethernet PHY, based on FXEDP110HC0A HJ026a and add 100BASE-FX feature....

300 0.118

10BASE-T/100BASE-TX/100BASE-FX/1000BASE-T Gigabit Energy Efficient Ethernet PHY; UMC 28nm HPC/Low-K process 10BASE-T/100BASE-TX/100BASE-FX/1000BASE-T Gigabit Energy Efficient Ethernet PHY; UMC 28nm HPC/Low-K process...