301 0.118

10BASE-T/100BASE-TX/100BASE-FX/1000BASE-T Gigabit Energy Efficient Ethernet PHY; UMC 28nm HPC+/LOW_K process 10BASE-T/100BASE-TX/100BASE-FX/1000BASE-T Gigabit Energy Efficient Ethernet PHY; UMC 28nm HPC+/LOW_K process...

302 0.118

Voltage mode 10/100 Base-TX/FX Energy Efficient Ethernet PHY; Support EtherCAT and cable diagnostic; UMC 0.11um HS/AE Logic Process. Voltage mode 10/100 Base-TX/FX Energy Efficient Ethernet PHY; Support EtherCAT and cable diagnostic; UMC 0.11um HS/AE Logic Process....

303 0.118

10/100/1000 ETHERNET CONTROLLER_x005F_x005F_x005F_x005F_x005F_x000D_ WITH AHB AND AXI BUS_x005F_x005F_x005F_x005F_x005F_x000D_ 10/100/1000 ETHERNET CONTROLLER WITH AHB AND AXI BUS...

304 0.118

10/100 Ethernet PHY IP, Energy Efficient, UMC 0.11um HS/AE process 10/100 Base-TX/FX Energy Efficient Ethernet PHY, UMC 0.11um HS/AE (AL Advance Enhancement) Logic process....

305 0.118

10/100 Ethernet PHY IP, UMC 65nm SP process 10/100 Base-TX Fast Ethernet PHY, UMC 65nm SP/RVT Low-K Logic process....

306 0.118

10BASE-Te/100BASE-TX/100BASE-FX/1000BASE-T Energy Efficient Ethernet PHY; UMC 28nm HPC+ process 10BASE-Te/100BASE-TX/100BASE-FX/1000BASE-T Energy Efficient Ethernet PHY; UMC 28nm HPC+ process...

307 0.118

Ethernet MAC IP, 10/100/1G Ethernet MAC, DMA (Direct Memory Access) function embedded, Soft IP 10/100/1000 Ethernet Controller with AHB bus....

308 0.118

Ethernet MAC IP, 10/100 Ethernet MAC, Soft IP 10/100 Ethernet MAC with MII or RMII (Reduced MII) interface....

309 0.0

320Gbps Ethernet Switch Packet Architects offers a series of high speed switching IPs which are developed using the unique FlexSwitch toolchain. The toolchain allows a fast a...

310 0.0

1G/10G/25G/50G/100G Ethernet Switch IP Core - Efficient and Massively Customizable Packet Architects offers a series of high speed switching IP cores, developed using the unique FlexSwitch toolchain. This toolchain provides a fast an...

311 0.0

Ethernet Switch / Router IP Core - Efficient and Massively Customizable Packet Architects offers a series of high speed switching/routing IP cores developed using the unique FlexSwitch tool-chain. This allows us to provide...

312 0.0

Gigabit Ethernet Media Access Controller Implements an Ethernet Media Access Controller compatible with the 10/100 Mbps IEEE 802.3 and 1Gbps IEEE 802.3-2002 specifications. The controller pro...

313 0.0

GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in SAM 14LPP The GPHY is a fully integrated IP Core with low power consumption for Giga 10/100/1000 Ethernet applications. It can operate in 10BASE-T, 100BASE-TX, ...

314 0.0

D-MAC-10/100 Our innovative solution is a hardware implementation of media access control protocol defined by the IEEE standard. DMAC in cooperation with external ...

315 0.0

Used for controlling HDLC/SDLC transmission protocols The DHDLC IP Core provides versatile support for a widely used HDLC transmission protocol. It manages the bit stuffing process, both address appending...

316 0.0

Serial Peripheral Interface – Master/Slave with Octal, Quad, Dual and Single SPI Bus support The SPI IP is a revolutionary octal SPI designed to offer the fastest operations available for any serial SPI memory. It is flexible enough to interfa...

317 0.0

QSPI FLASH Controller – XIP functionality (SINGLE, DUAL and QUAD SPI Bus Controller with Double Data Rate support) The SPI is a fully configurable SINGLE, DUAL, QUAD and OCTAL SPI master/slave device, which allows user to configure polarity and phase of serial cloc...

318 0.0

GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in UMC 28HPC The GPHY is a fully integrated single chip for Gigabit Ethernet applications with lowest power consumption. It is capable of functioning in 10BASE-T, ...

319 0.0

Gigabit Ethernet 802.3 MAC Controller IP The Giga MAC IP is an embedded Fast Ethernet controller module. It is compliant with IEEE 802.3 specification for 10/100Mbps Ethernet and the IEEE802....

320 0.0

DVB-S2X WideBand Demodulator & Decoder IP (Silicon Proven) This is a high-performance, dual high-symbol-rate (HSR) DVB-S2/S2X demodulator IP extarcted from production chipsets with integrated tuner and silcon ...

321 0.0

DVB-S2X WideBand Demodulator IP This is a high-performance, dual high-symbol-rate (HSR) DVB-S2/S2X demodulator IP extarcted from production chipsets with integrated tuner and silcon ...

322 0.0

DVB-S2X LDPC/BCH Decoder IP (Silicon Proven) The DVB-S2/S LDPC/BCH decoder a silicon proven IP extracted from production chips has an octal input interface and a single output interface. The data...

323 0.0

DVB-S2X NarrowBand Demodulator IP This is NarrowBand demodulator IP is silicon proven and extratced from production chipsets, it performs demodulation according to DVB-S, legacy Direct...

324 0.0

Networking SerDes IP, Silicon Proven in ST 28FDSOI The 28 Gbps SerDes PHYs are comprehensive IP solutions that deliver enterprise-class performance across the challenging signaling environments typical...

325 0.0

ISDB-S3-LDPC-BCH Decoder IP This design is a ISDB-S3-LDPC-BCH Decoder IP, ready to license, verified and packaged, and supplied as a portable and synthesizable Verilog IP. The sy...

326 0.0

BCH Decoder IP The BCH decoder has four main functional blocks along with memory blocks. Syndrome calculation block calculates syndrome components which tell about p...

327 0.0

LDPC Decoder IS-GPS-800D IP The IS-GPS-800D standard defines an irregular Parity Check Matrix (PCM) for 2 subframes (2 and 3) encoded using Low Density Parity Check (LDPC) Forwar...

328 0.0

DVB-T2/Lite LDPC Decoder IP In Digital video broadcasting for terrestrial broadcasting systems, a powerful FEC sub-system is needed. FEC is based on LDPC (Low-Density Parity Chec...

329 0.0

DVB-S2X-LDPC Decoder IP In Digital video broadcasting for digital transmission for satellite applications, a powerful FEC sub-system is needed. FEC is based on LDPC (Low-Dens...

330 0.0

DVB-S2-LDPC-BCH IP The DVB-S2-LDPC-BCH block is a powerful FEC (Forward Error Correction) subsystem for Digital Video Broadcasting via Satellite. In Digital video broad...

331 0.0

DVB-T2-LDPC-BCH IP In Digital video broadcasting for digital transmission for satellite applications, a powerful FEC (Forward Error Correction) sub-system is needed. FEC...

332 0.0

DVB-C2 LDPC Decoder IP The Digital video broadcasting for cable systems systems, a powerful FEC sub-system is needed. FEC is based on LDPC (Low-Density Parity Check) codes c...

333 0.0

Viterbi Decoder Convolutional FEC codes are very popular because of their powerful error correction capability and are especially suited for correcting random errors....

334 0.0

GbE (10/100 Base-T) PHY IP, Silicon Proven UMC 28HPC Ethernet PHY is an IEEE 802.3u compliant single-port Ethernet physical layer transceiver, and low power consumption transceiver for 10BASE-Te, 100BASE...

335 0.0

GbE (10/100 Base-T) PHY IP, Silicon Proven UMC 40LP An IEEE 802.3u compliant single-port Ethernet physical layer transceiver with low power consumption for 10BASE-Te and 100BASE-TX operation is known as...

336 0.0

Nonbinary LDPC Decoder A powerful Forward Error Correction (FEC) subsystem is needed in almost all wireless communication systems. Low-Density Parity-Check (LDPC) codes are ...

337 0.0

Reed Solomon The Reed Solomon Encoder is fed with an input message of K information symbols, the Encoder appends 2T parity symbols to the input message in order to...

338 0.0

LTE Turbo Decoder In order to achieve higher throughput, the turbo decoder uses up to 8-parallel MAP decoder. The sliding window algorithm is used to reduce the interna...

339 0.0

Flash Memory LDPC LDPC corrects errors caused by flash storage failure mechanisms. The data is encoded while writing into the storage devices and it is decoded while re...

340 0.0

CCSDS AR4JA LDPC Encoder/Decoder AR4JA LDPC decoder is a configurable design that allows runtime configuration for decoding different code rates (i.e., 1/2, 2/3, and 3/4). To obtain h...

341 0.0

HDMI 2.1 Forward Error Correction (FEC) Transmitter The HDMI Forward Error Correction (FEC) Transmitter IP Core implements Reed-Solomon FEC and symbol mapping/interleaving as specified by the HDMI 2.1 ...

342 0.0

NCR Processor NCR (Network Clock Reference) is a procedure to provide the master clock (i.e. time information) of the satellite to all its user terminals. Typically...

343 0.0

VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter The DisplayPort Forward Error Correction (FEC) Transmitter IP core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA Displa...

344 0.0

10Gbit/s Ethernet UDT Server for FPGAs FPGA Synthesisable 10Gbit/s Ethernet UDT4 server for reliable long distance/high bandwidth data transfer...

345 0.0

ARP/ICMP Protocol for Ethernet The CT1006-XGARP/ICMP block adds RTL-hardened functions for ICMP and ARP to any FPGA application. The all-RTL block includes part of the ARP protoc...

346 0.0

25Gbit/s Ethernet MAC The Chevin Technology 25GMAC IP core provides Ultra Low-Latency 25Gbit/s Ethernet connectivity in Xilinx Virtex® UltraScale™ FPGAs. The 25GMAC can...

347 0.0

25Gbit/s Ethernet PCS The Chevin Technology 25GPCS provides Ultra low-latency 25Gbit/s Ethernet connectivity in Xilinx Virtex® UltraScale™ FPGAs. Ultra-low latency is achie...

348 0.0

25G LL MAC /PCS Ethernet IP for FPGA The Chevin Technology 25G LL MAC/PCS combines the 25G MAC and 25G PCS IP cores to obtain the lowest possible latency while simplifying the integration...

349 0.0

5/10/40G Ultra Low Latency MAC PCS with AXI-4 and UCIe support This IP is optimized for AI/ML workloads and lowest possible latency. It is not meant to be a generic 1G to 10G MAC – it only supports 5G and 10G oper...

350 0.0

DVB-S2X Modulator IP Core IP core has two ways of forming the output spectrum: -Baseband (using odati and odatq), ifreq equal 0 -Intermediate frequency (using odati), ifreq not...