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7 IP
1
10.0
MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A, N3A)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
2
0.0
MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in GlobalFoundries (12nm) for Automotive
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
3
0.0
MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in Samsung (SF5A, SF4A) for Automotive
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
4
0.0
MIPI C-PHY v2.0 D-PHY v2.1 RX 3 trios/4 Lanes in TSMC (N7, N5A, N3A)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
5
0.0
MIPI C-PHY v2.0 D-PHY v2.1 TX 2 trios/2 Lanes in TSMC (N7) for Automotive
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
6
0.0
MIPI C-PHY v2.0 D-PHY v2.1 TX 3 trios/4 Lanes in Samsung (SF5A, SF4A) for Automotive
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
7
0.0
MIPI C-PHY v2.0 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (N7)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
