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Industry Articles
The Age of the Monster Chip
(Wednesday, September 18, 2019)
Better Benchmarks through Compiler Optimizations: Codasip Jump Threading
(Monday, September 9, 2019)
The Gatekeeper of a Successful Design is the Interconnect
(Tuesday, September 3, 2019)
UVM RAL Model: Usage and Application
(Monday, September 2, 2019)
Re-Architecting SoCs for the AI Era
(Monday, August 26, 2019)
Improving design routability and timing by smart port reduction and placement technique
(Monday, August 19, 2019)
Time Sensitive Networking: An Introduction to TSN
(Monday, July 29, 2019)
Configure, Confirm, Ship: Build Secure Processor-Based Systems with Faster Time-to-Market
(Monday, July 29, 2019)
How to use snakes to speed up software without slowing down the time-to-market?
(Monday, July 22, 2019)
NVMe/TCP Improves Data Storage
(Monday, July 1, 2019)
Enhancing privacy and security in the smart meter lifecycle
(Thursday, June 27, 2019)
Choosing a Processor for Machine Learning at the Edge
(Monday, June 24, 2019)
Deliver "Smarter" Faster: Design Methodology for AI/ML Processor Design
(Thursday, June 20, 2019)
Testing Of Repairable Embedded Memories in SoC: Approach and Challenges
(Monday, June 17, 2019)
SoC Interconnect: Don't DIY!
(Thursday, June 13, 2019)
Understanding - and Reducing - Latency in Video Compression Systems
(Monday, June 3, 2019)
Extending RISC-V ISA With a Custom Instruction Set Extension
(Monday, June 3, 2019)
Dual Mode C-PHY/D-PHY: Enabling Next Generation of VR Displays
(Tuesday, May 28, 2019)
Enabling Composable Platforms with On-Chip PCIe Switching, PCIe-over-Cable
(Tuesday, May 28, 2019)
New AI Computing in Consumer Electronics
(Monday, May 20, 2019)
Increase battery life of Consumer Products using architecture simulation
(Thursday, May 16, 2019)
Area Overhead: GOH Control and Track
(Tuesday, May 14, 2019)
Distorted Waveform Phenomena in 7nm Technology Node and its Impact on Signoff Timing Analysis
(Monday, May 6, 2019)
AI Challenges for Next-Gen EDA
(Friday, May 3, 2019)
EDA Finds a Common Framework for AI
(Monday, April 29, 2019)
It's Not My Fault! How to Run a Better Fault Campaign Using Formal
(Monday, April 29, 2019)
Image Processing - RTL Implementation of Median Filtering for Image Denoising
(Thursday, April 25, 2019)
Integrated ADAS Domain Controller SoCs with ISO 26262 Certified IP
(Monday, April 22, 2019)
System Verilog Macro: A Powerful Feature for Design Verification Projects
(Friday, April 19, 2019)
Creating SoC Integration Tests with Portable Stimulus and UVM Register Models
(Monday, April 15, 2019)
Memory Testing - An Insight into Algorithms and Self Repair Mechanism
(Monday, April 8, 2019)
Verify Smarter, Not Harder
(Thursday, April 4, 2019)
Signoff Iteration Reduction Technique for Fixing Top Level Antenna
(Monday, April 1, 2019)
Guide to Choosing the Best DCDC Converter for Your Application
(Monday, March 25, 2019)
Guide to Choosing the Best DC-to-DC Converter for Your Application
(Monday, March 25, 2019)
A Heuristic Approach to Fix Design Rule Check (DRC) Violations in ASIC Designs @7nm FinFET Technology
(Monday, March 25, 2019)
Which DDR SDRAM Memory to Use and When
(Monday, March 18, 2019)
Integration of power:communication interfaces in smart true wireless headset designs
(Wednesday, March 13, 2019)
Nucleus SE RTOS initialization and start-up
(Wednesday, March 13, 2019)
SOC Stability in a Small Package
(Monday, March 11, 2019)
Reducing DFT Footprints: A Case in Consumer SoC
(Monday, March 11, 2019)
Hidden Signals: The Memories and Interfaces Enabling IoT, 5G, and AI
(Monday, March 11, 2019)
PCIe 5.0 vs. Emerging Protocol Standards - Will PCIe 5.0 Become Ubiquitous in Tomorrow's SoCs?
(Monday, March 4, 2019)
Right-Sizing Your Cryptographic Processing Solution
(Monday, March 4, 2019)
Cost Reduction and Improved TTR with Shared Scan-in DFT CODEC
(Monday, February 25, 2019)
Creating a custom processor with RISC-V
(Monday, February 18, 2019)
Guide to Choosing the Best LDO for Your Application
(Monday, February 18, 2019)
Guide to Choosing the Best LDO for Your Application
(Monday, February 18, 2019)
A Guide on Logical Equivalence Checking - Flow, Challenges, and Benefits
(Tuesday, February 12, 2019)
Transitioning from DDR4 to DDR5 DIMM Buffer Chipsets
(Thursday, February 7, 2019)
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