Company
design-reuse.com
D&R China
Blogs
Industry Articles
D&R Events
IP-SoC Days 2026
IP-SoC Days 2025
IP-SoC Days 2024
IP-SoC Days 2023
IP-SoC Days 2022
IP-SoC 2025
IP-SoC 2024
IP-SoC 2023
IP-SoC 2022
Videos
Subscribe to D&R SoC News Alert
English
Mandarin
Login
Catalog of SIP Cores
System on Chip design resources
Catalog of SIP Cores
System on Chip design resources
Menu
Home
Search IP Core
News
Blogs
Articles
D&R Events
Videos
Subscribe to D&R SoC News Alert
Login
News
Center
Foundation IP
Analog IP
Interface IP
Interconnect IP
Memory Controller & PHY
Peripheral Controller
Wireless IP
Wireline IP
Processor IP
RISC-V
AI Core
Automotive IP
Security IP
IoT
Media IP
Avionics / Space IP
Verification IP
Verification Platform
Design Platform
Asic & IP Design Center
IP-SoC Days
IP-SoC Days 2026
IP-SoC Days 2025
IP-SoC Days 2024
IP-SoC Days 2023
IP-SoC Days 2022
IP-SoC 2025
IP-SoC 2024
IP-SoC 2023
IP-SoC 2022
Industry Articles
Performance verification of a complex bus arbiter using the VMM Performance Analyzer
(Thursday, September 23, 2010)
Desperately Seeking Solutions to the verification nightmare
(Wednesday, September 22, 2010)
How to make virtual prototyping better than designing with hardware: Part 1
(Wednesday, September 22, 2010)
A closer look at analog verification
(Friday, September 17, 2010)
The basics of SerDes (serializers/deserializers) for interfacing
(Friday, September 17, 2010)
How to achieve 1 trillion floating-point operations-per-second in an FPGA
(Wednesday, September 15, 2010)
Conquering the memory bottleneck
(Tuesday, September 14, 2010)
Power-efficient SDR platform handles multimode 4G
(Tuesday, September 14, 2010)
How to Internet-Connect your low cost consumer retail embedded design
(Tuesday, September 14, 2010)
Hardware - Software Tradeoffs in Automotive Sensor Data Processing
(Monday, September 13, 2010)
Do we need an international EDA roadmap?
(Thursday, September 9, 2010)
Debugging the Linux kernel with JTAG
(Tuesday, September 7, 2010)
Accelerating the Development of TLM-2.0 Models Using Model Authoring Kits (MAKs)
(Monday, September 6, 2010)
Evaluating platform software architectures for nextgen embedded multicore designs
(Wednesday, September 1, 2010)
Power Management: Designing from a System-level Perspective
(Tuesday, August 31, 2010)
Dual core architectures in automotive SoCs
(Thursday, August 26, 2010)
How audio processing algorithms help improve sound from small speakers
(Thursday, August 26, 2010)
Extreme Design: Realizing a single-chip CMOS 56 Gs/s ADC for 100 Gbps Ethernet
(Thursday, August 26, 2010)
Commentary: How strong are your IP assets?
(Thursday, August 26, 2010)
Harness speed, performance, signal integrity, and low current advantages of 65nm QDR family SRAMs
(Tuesday, August 24, 2010)
Reusable Device Simulation Models for Embedded System Virtual Platforms
(Monday, August 23, 2010)
System Verilog configurable coverage model in an OVM setup - concept of reusability
(Monday, August 23, 2010)
How throughput enhancements dramatically boost 802.11n MAC efficiency--Part II
(Thursday, August 19, 2010)
Using switched capacitors to create programmable analog logic blocks in mixed-signal designs
(Wednesday, August 18, 2010)
Reusability, usability and flexibility
(Wednesday, August 18, 2010)
How to use FireWire for innovative new designs without distance constraints
(Wednesday, August 18, 2010)
A case for not choosing the latest components
(Wednesday, August 18, 2010)
Comparing AMBA AHB to AXI Bus using System Modeling
(Thursday, August 12, 2010)
How throughput enhancements dramatically boost 802.11n MAC efficiency--Part I
(Wednesday, August 11, 2010)
Reduce embedded SoC design cost & optimize IP integration
(Tuesday, August 10, 2010)
FPGA compilation on-site or in the cloud
(Monday, August 9, 2010)
Picking the right built-in self-test strategy for your embedded ASIC
(Thursday, August 5, 2010)
Use XML to build ASIC or SoC design specifications
(Wednesday, August 4, 2010)
Using in-design physical verification to reduce tapeout schedules
(Monday, August 2, 2010)
The ripple effect
(Thursday, July 29, 2010)
Generating AMD microcode stimuli using VCS constraint solver
(Monday, July 26, 2010)
Protect your goal with post-silicon formal verification
(Friday, July 23, 2010)
Give the people what they want: HLS for RTL verification
(Wednesday, July 21, 2010)
Real Time Non-intrusive Debugging Framework
(Monday, July 19, 2010)
Customized FPGA board for ASIC Prototyping - A novel approach with Predesigned Blocks and Modular FPGA
(Thursday, July 15, 2010)
MIPI M-PHY takes center stage
(Tuesday, July 13, 2010)
SuperSpeed USB (USB 3.0): More than just a speed increase
(Monday, July 12, 2010)
Can MIPI and MDDI Co-Exist?
(Friday, July 9, 2010)
How productive is your R&D organization?
(Thursday, July 1, 2010)
Efficient 'C' Programming and its Effect on the Performance of Embedded Systems
(Monday, June 28, 2010)
How to make virtual prototyping better than designing with hardware: Part 2
(Wednesday, June 23, 2010)
How to make virtual prototyping better than designing with hardware: Part 1
(Wednesday, June 23, 2010)
Multiplexed Energy Metering AFEs Ease ASIC Integration and Provide Significant Cost Reduction
(Monday, June 21, 2010)
System Verilog based Generic Verification Methodology for IPs/ASICs/SOCs: A Case Study
(Monday, June 21, 2010)
Viewpoint: Debug will get your attention, sooner or later
(Thursday, June 17, 2010)
|
Previous
|
43
|
44
|
45
|
...
|
Next
|
Previous
