Search News

Design Platform News

• 'World-Leading' Semiconductor Design Centre Will 'Strengthen Wales' Leadership in Chip Design' (Sunday, March 23, 2025)
• Siemens Xcelerator: Siemens accelerates IT and OT integration with Microsoft for Edge, Cloud, AI and Simulation (Wednesday, March 19, 2025)
• Synopsys: Autonomous AI Agents to Tame Chip Design Complexity (Wednesday, March 19, 2025)
• Sofics and Dolphin Semiconductor Announce Strategic Partnership (Tuesday, March 18, 2025)
• Cadence Accelerates AI-Driven Engineering Design and Science with NVIDIA Grace Blackwell (Monday, March 17, 2025)
• Synopsys Accelerates Chip Design with NVIDIA Grace Blackwell and AI to Speed Electronic Design Automation (Monday, March 17, 2025)
• Pragmatic launches platform for mixed-signal flexible ASIC design (Wednesday, March 5, 2025)
• Renesas and Altium Announce Introduction of Renesas 365, Powered by Altium: Groundbreaking Industry Solution for Software-Defined Products (Wednesday, March 5, 2025)
• Arm Compute Platform at the Heart of Malaysia's Silicon Vision (Tuesday, March 4, 2025)
• Pragmatic Semiconductor launches next-generation platform for mixed-signal flexible ASIC design with early-access programme (Tuesday, March 4, 2025)
• Marvell Demonstrates Industry's Leading 2nm Silicon for Accelerated Infrastructure (Sunday, March 2, 2025)
• Arteris Releases the Latest Generation of Magillem Registers to Automate Semiconductor Hardware/Software Integration (Monday, February 24, 2025)
• AccelerComm® announces 5G NR NTN Physical Layer Solution that delivers over 6Gbps, 128 beams and 4,096 user connections per chipset (Monday, February 17, 2025)
• Mirabilis Design Accelerates SoC Development with New System-Level IP Library for Cadence Tensilica Processors (Sunday, February 16, 2025)
• Qualitas Semiconductor entered into IP Licensing Agreement with a Leading Korean System Semiconductor Design Company (Thursday, February 13, 2025)
• New Memory Architectures for SoCs and Multi-Die Systems (Wednesday, February 12, 2025)
• Synopsys Expands the Industry's Highest Performance Hardware-Assisted Verification Portfolio to Propel Next-Generation Semiconductor and Design Innovation (Wednesday, February 12, 2025)
• Siemens to accelerate customer time to market with advanced silicon IP through new Alphawave Semi partnership (Tuesday, February 11, 2025)
• Groundbreaking Formal Verification Further Enhances the Quality of CHERIoT-Ibex (Monday, February 10, 2025)
• Onsemi's Treo Taps Weebit ReRAM (Sunday, February 9, 2025)
• QuickLogic Integrates Synopsys Synplify Synthesis for Best-in-Class Quality of Results (Sunday, February 9, 2025)
• CEA-Leti Announces FAMES Pilot Line in Nature Reviews Electrical Engineering (Sunday, February 9, 2025)
• Axiomise Launches footprint, Area Analyzer for Silicon Design (Wednesday, February 5, 2025)
• Cadence Virtuoso Studio advanced optimization enhances MediaTek's efficiency by 30% (Tuesday, February 4, 2025)
• Accellera Board Approves Universal Verification Methodology for Mixed-Signal (UVM-MS) 1.0 Standard for Release (Tuesday, February 4, 2025)
• Alchip opens 3DIC ASIC design services (Thursday, January 16, 2025)
• Alchip opens 3DIC ASIC design services (Thursday, January 16, 2025)
• Exostiv Labs Unveils AMD Versal Adaptive SoC Device Support for Exostiv and Exostiv Blade Platforms (Sunday, January 12, 2025)
• Qualitas Semiconductor and Verisilicon signed a licensing agreement for 4nm PCIe 6.0 PHY IP (Wednesday, January 8, 2025)
• Cadence: Leading the EDA Industry with AI-Powered Platforms (Tuesday, January 7, 2025)
• Siemens Xcelerator: Eplan and Siemens Enable Data Interoperability in Machine Engineering (Thursday, January 2, 2025)
• EnSilica PLC Demonstrates Strong Growth and Market Position in ASIC Industry (Friday, December 27, 2024)
• GUC Joins Arm Total Design Ecosystem to Strengthen ASIC Design Services (Monday, December 23, 2024)
• Siemens extends Veloce hardware-assisted verification support of EPGM Ethernet to 1.6 Tbps (Tuesday, December 17, 2024)
• sureCore teams with Sarcina to package cryo chips (Monday, December 16, 2024)
• MosChip selects Cadence tools for the design of HPC Processor "AUM" for C-DAC (Wednesday, December 11, 2024)
• MosChip selects Cadence tools for the design of HPC Processor "AUM" for C-DAC (Tuesday, December 10, 2024)
• Silvaco Joins SMART USA Institute to Propel Digital Twin Innovations Under CHIPS Manufacturing USA Program (Tuesday, December 3, 2024)
• Marvell Unveils Industry's First 3nm 1.6 Tbps PAM4 Interconnect Platform to Scale Accelerated Infrastructure (Monday, December 2, 2024)
• Arteris Deployed by Menta for Edge AI Chiplet Platform (Monday, December 2, 2024)
• HPC customer engages Sondrel for high end chip design (Thursday, November 21, 2024)
• Solid Sands and VyperCore Collaborate to Ensure C/C++ Compliance in New Accelerator Chip Design (Wednesday, November 20, 2024)
• Renesas Introduces Industry's First Complete Memory Interface Chipset Solutions for Second-Generation DDR5 Server MRDIMMs (Tuesday, November 19, 2024)
• NVIDIA Announces Omniverse Real-Time Physics Digital Twins With Industry Software Leaders (Sunday, November 17, 2024)
• Siemens Launches TIA Portal Version 20 Focused on Improved Performance (Friday, November 15, 2024)
• Siemens presents next-generation AI-supported software for electronic system design (Thursday, November 14, 2024)
• Siemens extends Veloce hardware-assisted verification and validation with new Innexis shift-left software (Monday, November 11, 2024)
• Oriole Networks Selects EnSilica as ASIC Partner and Contract Award for Photonics Controller ASIC (Sunday, November 10, 2024)
• Oriole Networks Selects EnSilica as ASIC Partner and Contract Award for Photonics Controller ASIC (Sunday, November 10, 2024)
• Siemens' Tessent In-System Test software enables advanced, deterministic testing throughout the silicon lifecycle (Monday, November 4, 2024)