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Design Platform News

• Launch of the New Horizon Europe Project SYCLOPS (Tuesday, May 9, 2023)
• Quantinuum's H2 quantum computer described as a significant step forward (Tuesday, May 9, 2023)
• Cryo-IP for quantum computing (Tuesday, May 9, 2023)
• OPENEDGES' 12nm LPDDR5/4x/4 PHY is Ready for Mass Production by Novachips' SSD (Tuesday, May 9, 2023)
• TSMC Teams Up With EDA Companies to Speed Up Design Flows (Tuesday, May 2, 2023)
• Alps Alpine uses Siemens Symphony to verify mixed-signal touch chip (Monday, May 1, 2023)
• PsiQuantum Expands Development Engagement and Plan for Production Ramp of Quantum Computing Technology at SkyWater's Minnesota Fab (Monday, May 1, 2023)
• M31 demonstrates high-speed interface IP development achievements on TSMC's 7nm & 5nm process technologies (Wednesday, April 26, 2023)
• Cadence Delivers New Design Flows Based on the Integrity 3D-IC Platform in Support of TSMC 3Dblox™ Standard (Wednesday, April 26, 2023)
• HDL Design House develops its first full SoC from architecture definition to tapeout for an external customer (Wednesday, April 26, 2023)
• High-precision microsensor technology for a wide application range (Tuesday, April 25, 2023)
• Cadence Delivers New Design Flows Based on the Integrity 3D-IC Platform in Support of TSMC 3Dblox™ Standard (Tuesday, April 25, 2023)
• Fraunhofer IIS/EAS Selects Achronix Embedded FPGAs (eFPGAs) to Build Heterogeneous Chiplet Demonstrator (Tuesday, April 25, 2023)
• Cadence Custom Design Migration Flow Accelerates Adoption of TSMC N3E and N2 Process Technologies (Monday, April 24, 2023)
• Synopsys and TSMC Collaborate to Jumpstart Designs on TSMC's N2 Process with Optimized EDA Flows (Monday, April 24, 2023)
• Agile Analog launches innovative digitally wrapped analog IP subsystems (Monday, April 24, 2023)
• OPENEDGES' 12nm LPDDR5/4 Memory Subsystem IP that Drives Innovation Licensed by ASICLAND (Monday, April 24, 2023)
• Arm reportedly developing 'advanced' test chip for customers (Sunday, April 23, 2023)
• Introducing High-Speed Fractional PLL IP Cores with SSC that offers exceptional features in different process technologies (Sunday, April 23, 2023)
• Omni Design's High Performance Analog Front Ends are Adopted in Socionext's Next Generation Communications SoCs (Saturday, April 22, 2023)
• Europe consolidates quantum production and test (Tuesday, April 18, 2023)
• Mixel MIPI C-PHY/D-PHY Combo IP Integrated into Hercules Microelectronics HME-H3 FPGA (Monday, April 17, 2023)
• Rapid Silicon Partners with Elastics.cloud on CXL 3.0 Dual Mode Controller IP to Enhance its Custom FPGA Solutions (Monday, April 17, 2023)
• Cadence Demonstrates Interoperability with SK hynix's Highest Speed LPDDR5T Mobile DRAM at 9600Mbps (Monday, April 17, 2023)
• Cadence Extends Collaboration with TSMC and Microsoft to Advance Giga-Scale Physical Verification in the Cloud (Sunday, April 16, 2023)
• Cadence Introduces EMX Designer, Delivering More Than 10X Increased Performance for On-Chip Passive Component Synthesis (Thursday, April 13, 2023)
• JEDEC Expands CAMM Standardization to include Two Key Memory Technologies (Wednesday, April 12, 2023)
• EnSilica evaluation platform for EN62020 sensor interface ASIC speeds up development of wearable fitness and healthcare sensor devices (Wednesday, April 12, 2023)
• Synopsys Introduces the Industry's First Emulation System with Unmatched Capacity to Enable Electronics Digital Twins of Advanced SoCs (Wednesday, April 12, 2023)
• Rapid Silicon Launches Revolutionary RapidGPT for FPGA Designers (Monday, April 10, 2023)
• CXL Testing Leverages PCIe Expertise (Wednesday, April 5, 2023)
• Rapidus, Japan's newly founded chip manufacturer, joins imec's Core Partner Program (Tuesday, April 4, 2023)
• Orthogone and Napatech collaborate to deliver state-of-the-art, ultra-low latency FPGA-based SmartNIC platform for high-frequency trading applications (Tuesday, April 4, 2023)
• CEO interview: Paul Wells of SureCore on low power memory and China (Monday, April 3, 2023)
• sureCore pushes the SRAM voltage envelope to below 0.5V for the first time (Monday, April 3, 2023)
• Sondrel signs EDA license extension with Siemens for three more years (Monday, April 3, 2023)
• I hear you NOCing, But Can You Close Timing? (Tuesday, March 28, 2023)
• Mobiveil's PSRAM Controller IP Lets SoC Designers Leverage AP Memory's Xccela x8/x16 250 MHz PSRAM Memory (Monday, March 27, 2023)
• China forms its own chiplet standard amid isolation (Sunday, March 26, 2023)
• OPENEDGES Completes the Tapeout of the 7nm HBM3 Memory Subsystem (PHY & Memory Controller) Test chip (Wednesday, March 22, 2023)
• Omni Design Opens Design Center in Hyderabad, India (Monday, March 20, 2023)
• Agile Analog joins Intel Foundry Services Accelerator IP Alliance Program to drive forward semiconductor design innovation (Monday, March 20, 2023)
• Securing Memory will Take More than Cryptography Alone (Sunday, March 19, 2023)
• Introducing Signature IP Corporation - Providing a Configurable And Flexible Platform for SoC Development (Tuesday, March 14, 2023)
• proteanTecs Collaborates with BAE Systems to Enable a Zero Trust Supply Chain for Defense Applications (Tuesday, March 14, 2023)
• Create high-performance SoCs using network-on-chip IP (Sunday, March 12, 2023)
• Arm and ecosystem leaders empower developers for a future built on Arm (Thursday, March 9, 2023)
• AmberSemi Announces Successful Tapeout of Silicon Chip for Patented AC Direct DC Power Delivery Technology (Thursday, March 9, 2023)
• Defacto's SoC Compiler 10.0 is Released (Wednesday, March 8, 2023)
• sureCore announces range of off-the-shelf, ultra-low power memory IP to help fast-track power critical designs (Tuesday, March 7, 2023)