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Design Platform and Service News

• Mobiveil and InPsytech Announce Successful Inter-Op Verification of Enterprise Flash Controller Design IP and ONFI 5.1 PHY IP (Monday, July 24, 2023)
• Cadence RTL design tool claims 5x faster RTL convergence (Sunday, July 23, 2023)
• 12bit 640Msps Dual-Channel IQ ADC High-Speed/High-Performance IP Cores for WiFi RF SoC is available for immediate licensing (Sunday, July 23, 2023)
• The revolutionary potential of 3D IC technology in the semiconductor ecosystem (Thursday, July 20, 2023)
• Synopsys Accelerates Advanced Chip Design with First-Pass Silicon Success of IP Portfolio on TSMC 3nm Process (Wednesday, July 19, 2023)
• Minimize Design Risk and Achieve First-Pass Silicon Success on TSMC's N3E Process (Tuesday, July 18, 2023)
• Lightelligence Partners With ZeroPoint Technologies to Increase Data Center Connectivity Performance by Up to 50% (Tuesday, July 18, 2023)
• Cadence Joules RTL Design Studio delivers breakthrough gains (Sunday, July 16, 2023)
• Cadence Unveils Joules RTL Design Studio, Delivering Breakthrough Gains in RTL Productivity and Quality of Results (Sunday, July 16, 2023)
• Global Semiconductor Equipment Sales Forecast: $87 Billion in 2023 With 2024 Rebound, SEMI Reports (Wednesday, July 12, 2023)
• Truechip Announces First Customer Shipment Of USB4v2 Verification IP (Wednesday, July 12, 2023)
• Faraday's Launched SerDes Advanced Service to Accelerate ASICs into Production (Monday, July 10, 2023)
• Synopsys Delivers Certified EDA Flows and High-Quality IP for Intel 16 Process (Monday, July 10, 2023)
• Siemens' Calibre platform now certified for IFS' Intel 16 process technology (Monday, July 10, 2023)
• Siemens unveils Calibre DesignEnhancer for Calibre correct-by-construction IC layout optimization (Sunday, July 9, 2023)
• Xpeedic Launches High-Speed Digital Signal Integrity, Power Integrity Suite at Design Automation Conference (Sunday, July 9, 2023)
• proteanTecs to Showcase the Future of Health and Performance Monitoring at DAC and SEMICON West 2023 (Tuesday, July 4, 2023)
• imec looks to process flow for sub-nm stacked CFET transistors (Tuesday, July 4, 2023)
• ADTechnology Joins Synopsys IP OEM Partner Program (Sunday, July 2, 2023)
• Synopsys and Golden Electronics Collaborate to Expand Chip Design Talent in Jordan (Sunday, July 2, 2023)
• Single Carrier Modem Available For Immediate Licensing From Global IP Core (Sunday, July 2, 2023)
• CAST Introduces New MACsec Protocol Engine IP Cores (Thursday, June 29, 2023)
• OKI IDS adopts Siemens Catapult High-Level Synthesis platform for design and verification services (Wednesday, June 28, 2023)
• Weebit Nano's ReRAM IP now fully qualified in SkyWater Technology's S130 process (Wednesday, June 28, 2023)
• Intel and Movellus Develop Different Fixes For IC Voltage Droop (Wednesday, June 28, 2023)
• Ansys and Synopsys Accelerate RFIC Semiconductor Design with New Reference Flow for Samsung Technology (Wednesday, June 28, 2023)
• Cadence Delivers Certified, Innovative Backside Implementation Flow to Support Samsung Foundry SF2 Technology (Tuesday, June 27, 2023)
• Cadence Digital and Custom/Analog Design Flows Certified for Samsung Foundry's SF2 and SF3 Process Technologies (Tuesday, June 27, 2023)
• DCAN FD Full - a final step to CAN XL? (Tuesday, June 27, 2023)
• With NextGen, CEA is inventing the future generations of electronic chips to maintain France's competitiveness (Monday, June 26, 2023)
• Cadence AI-Based Virtuoso Studio Certified for Samsung Foundry PDKs for Mature and Advanced Nodes (Monday, June 26, 2023)
• Comcores Unveils JESD204 IP Core Integration Guide to Streamline Customer PHY Integration Challenges (Monday, June 26, 2023)
• Arasan furthers the compliance of their I3C IP with its participation in the I3C Interop at MIPI Member Meeting (Monday, June 26, 2023)
• CXL: The key to memory capacity in next-gen data centers (Sunday, June 25, 2023)
• 12Bit ADC and DAC IP Cores with High-Speed, High-Performance for Wireless applications that requires RF are available for immediate licensing (Sunday, June 25, 2023)
• DB GlobalChip Deploys Cadence's Spectre FX and AMS Designer, Accelerating IP Verification by 2X (Sunday, June 25, 2023)
• Airbus and STMicroelectronics to develop silicon carbide power electronics for aircraft (Wednesday, June 21, 2023)
• OPENEDGES Achieves Tapeout of LPDDR5x/5/4x/4 PHY IP on 5nm SF5A Process Technology (Tuesday, June 20, 2023)
• Can Any Novel Architecture Topple the Mighty GPU? (Monday, June 19, 2023)
• Extending Moore's Law: CEA-Leti & Intel to Develop Atomically Thin 2D TMDs on 300mm Wafers Using Layer Transfer Technology for Future Transistor Scaling (Sunday, June 18, 2023)
• DFSPI IP Core from DCD supports all serial memories available on the market. (Thursday, June 15, 2023)
• M31 Has Expanded MIPI IP Portfolio, Successfully Validated 7nm MIPI C/D PHY Combo IP (Thursday, June 15, 2023)
• SK Powertech Adopts Silvaco's Victory TCAD Solution for the Development of Next Generation SiC Power Devices (Wednesday, June 14, 2023)
• Cadence Announces $200 Million Accelerated Share Repurchase Agreement (Wednesday, June 14, 2023)
• Nanusens secures first IP license for its revolutionary MEMS-in-ASICs™ sensor technology (Wednesday, June 14, 2023)
• Axiomose testimonial from AMD (Wednesday, June 14, 2023)
• Meeting the Major Challenges of Modern Memory Design (Wednesday, June 14, 2023)
• Leveraging IBIS-AMI Models to Optimize PCIe 6.0 Designs (Wednesday, June 14, 2023)
• Cadence and Samsung Foundry Enter Multi-Year Agreement to Expand Design IP Portfolio (Tuesday, June 13, 2023)
• PCI-SIG® Announces New Research Projecting PCI Express® Technology TAM Expected to Reach $10 Billion by 2027 (Tuesday, June 13, 2023)