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Design Platform and Service News

• OPENEDGES' 12nm LPDDR5/4 Memory Subsystem IP that Drives Innovation Licensed by ASICLAND (Monday, April 24, 2023)
• Arm reportedly developing 'advanced' test chip for customers (Sunday, April 23, 2023)
• Introducing High-Speed Fractional PLL IP Cores with SSC that offers exceptional features in different process technologies (Sunday, April 23, 2023)
• Omni Design's High Performance Analog Front Ends are Adopted in Socionext's Next Generation Communications SoCs (Saturday, April 22, 2023)
• Europe consolidates quantum production and test (Tuesday, April 18, 2023)
• Mixel MIPI C-PHY/D-PHY Combo IP Integrated into Hercules Microelectronics HME-H3 FPGA (Monday, April 17, 2023)
• Rapid Silicon Partners with Elastics.cloud on CXL 3.0 Dual Mode Controller IP to Enhance its Custom FPGA Solutions (Monday, April 17, 2023)
• Cadence Demonstrates Interoperability with SK hynix's Highest Speed LPDDR5T Mobile DRAM at 9600Mbps (Monday, April 17, 2023)
• Cadence Extends Collaboration with TSMC and Microsoft to Advance Giga-Scale Physical Verification in the Cloud (Sunday, April 16, 2023)
• Cadence Introduces EMX Designer, Delivering More Than 10X Increased Performance for On-Chip Passive Component Synthesis (Thursday, April 13, 2023)
• JEDEC Expands CAMM Standardization to include Two Key Memory Technologies (Wednesday, April 12, 2023)
• EnSilica evaluation platform for EN62020 sensor interface ASIC speeds up development of wearable fitness and healthcare sensor devices (Wednesday, April 12, 2023)
• Synopsys Introduces the Industry's First Emulation System with Unmatched Capacity to Enable Electronics Digital Twins of Advanced SoCs (Wednesday, April 12, 2023)
• Rapid Silicon Launches Revolutionary RapidGPT for FPGA Designers (Monday, April 10, 2023)
• CXL Testing Leverages PCIe Expertise (Wednesday, April 5, 2023)
• Rapidus, Japan's newly founded chip manufacturer, joins imec's Core Partner Program (Tuesday, April 4, 2023)
• Orthogone and Napatech collaborate to deliver state-of-the-art, ultra-low latency FPGA-based SmartNIC platform for high-frequency trading applications (Tuesday, April 4, 2023)
• CEO interview: Paul Wells of SureCore on low power memory and China (Monday, April 3, 2023)
• sureCore pushes the SRAM voltage envelope to below 0.5V for the first time (Monday, April 3, 2023)
• Sondrel signs EDA license extension with Siemens for three more years (Monday, April 3, 2023)
• I hear you NOCing, But Can You Close Timing? (Tuesday, March 28, 2023)
• Mobiveil's PSRAM Controller IP Lets SoC Designers Leverage AP Memory's Xccela x8/x16 250 MHz PSRAM Memory (Monday, March 27, 2023)
• China forms its own chiplet standard amid isolation (Sunday, March 26, 2023)
• OPENEDGES Completes the Tapeout of the 7nm HBM3 Memory Subsystem (PHY & Memory Controller) Test chip (Wednesday, March 22, 2023)
• Omni Design Opens Design Center in Hyderabad, India (Monday, March 20, 2023)
• Agile Analog joins Intel Foundry Services Accelerator IP Alliance Program to drive forward semiconductor design innovation (Monday, March 20, 2023)
• Securing Memory will Take More than Cryptography Alone (Sunday, March 19, 2023)
• Introducing Signature IP Corporation - Providing a Configurable And Flexible Platform for SoC Development (Tuesday, March 14, 2023)
• proteanTecs Collaborates with BAE Systems to Enable a Zero Trust Supply Chain for Defense Applications (Tuesday, March 14, 2023)
• Create high-performance SoCs using network-on-chip IP (Sunday, March 12, 2023)
• Arm and ecosystem leaders empower developers for a future built on Arm (Thursday, March 9, 2023)
• AmberSemi Announces Successful Tapeout of Silicon Chip for Patented AC Direct DC Power Delivery Technology (Thursday, March 9, 2023)
• Defacto's SoC Compiler 10.0 is Released (Wednesday, March 8, 2023)
• sureCore announces range of off-the-shelf, ultra-low power memory IP to help fast-track power critical designs (Tuesday, March 7, 2023)
• Orca Launches ORC5000 Platform for Low-Power ASIC Designs (Tuesday, March 7, 2023)
• Samsung Foundry, Anaflash partner on embedded flash memory (Monday, March 6, 2023)
• Weebit Nano ReRAM IP now available in SkyWater Technology's S130 process (Monday, March 6, 2023)
• Weebit Nano partners with University of Florida's Nino Research Group to examine effects of radiation on Weebit ReRAM (Monday, March 6, 2023)
• Sondrel extends multi-year, multi-million dollar EDA license with Synopsys (Monday, March 6, 2023)
• Tata Consultancy Services and Renesas Partner to Open Innovation Center to Develop Next-Generation Semiconductor Solutions (Sunday, March 5, 2023)
• OPENEDGES Announces LPDDR5X/5/4x/4 PHY Tapeout at 7nm process node (Sunday, March 5, 2023)
• Intel expands ecosystem with quantum computing SDK (Thursday, March 2, 2023)
• HDL Design House has opened New design center in Nis - Serbia (Wednesday, March 1, 2023)
• Floadia Completes eFlash IP Qualification on TSMC 130BCD plus Process and Achieves the World's Highest Data Retention for 10 Years at 200°C (Wednesday, March 1, 2023)
• Omni Design Technologies Awarded ISO 9001 Certification (Tuesday, February 28, 2023)
• Avery Design Debuts CXL Validation Suite (Monday, February 27, 2023)
• Mixel MIPI D-PHY IP Integrated into Teledyne e2v's new Topaz CMOS Image Sensors (Monday, February 27, 2023)
• MIPI Alliance Welcomes Google as a Promoter Member (Monday, February 27, 2023)
• Truechip Announces Early Adopter Version of Sub-System Verification IP (Monday, February 27, 2023)
• Agile Analog announces first customisable, process agnostic, 12-bit ADC IP (Monday, February 27, 2023)