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Design Platform and Service News

• USB 3.0 IP, MIPI D-PHY v1.2 IP, Display Port v1.4 IP, 1G Ethernet IP, the Best-Selling Interface IP Cores solutions through T2M in 2022 (Sunday, January 1, 2023)
• Digital Blocks DMA Controller Verilog IP Core Family Extends Leadership with enhancements to AXI4 Memory Map and Streaming Interfaces (Sunday, January 1, 2023)
• Taiwan Brings 96 Startups to Attend CES 2023 (Wednesday, December 28, 2022)
• €270m for RISC-V chiplets to build European exascale supercomputers (Wednesday, December 28, 2022)
• Quantum Computing Brings New Error Correction Challenges (Sunday, December 25, 2022)
• Cadence Announces Industry Best-In-Class 8533Mbps LPDDR5X IP Solution for Next-Generation AI, Automotive and Mobile Applications (Sunday, December 25, 2022)
• GbE (10/100/1000Base-T) PHY IP Core, a robust, low-power, fully featured IP Core along with MAC Controller IP Core is available for immediate licensing (Monday, December 19, 2022)
• DDMA, multi-channel DMA Controller IP core from DCD-SEMI (Wednesday, December 14, 2022)
• M3 Technology Receives EE Awards for Simplifying Supercapacitor Designs (Tuesday, December 13, 2022)
• JEDEC Publishes Automotive Solid State Drive (SSD) Device Standard (Tuesday, December 13, 2022)
• Cadence Wins Six 2022 TSMC OIP Partner of the Year Awards (Monday, December 12, 2022)
• Faraday Unveils SONOS eFlash Platform with Infineon on UMC 40uLP (Monday, December 12, 2022)
• Sofics joins the Intel Foundry Services (IFS) Accelerator IP Alliance program (Sunday, December 11, 2022)
• USB 3.2 OTG Controller and PHY IP Cores for ultra-high speed, lossless data and power delivery are available for immediate licensing (Sunday, December 11, 2022)
• Finland connects a quantum computer to a supercomputer (Monday, December 5, 2022)
• France's Siquance startup targets 'European' quantum computing (Monday, December 5, 2022)
• Avery Design Systems Announces SimXACT-SA™ for Improved Sequential X-Verification (Monday, December 5, 2022)
• Ansys Announces GlobalFoundries Certification of Semiconductor Tools for GF 22FDX® Platform (Sunday, December 4, 2022)
• Implement seamless DRAM processing speeds utilizing Silicon Proven DDR4/LPDDR4/DDR3L Combo PHY IP Core in 12FFC process technology (Sunday, December 4, 2022)
• Innovative ASIC CPU Drives Record-Setting Server Performance (Sunday, December 4, 2022)
• Siemens streamlines medical standards compliance for Linux OS based systems (Wednesday, November 30, 2022)
• QuantWare launches Foundry Services for superconducting quantum chips (Monday, November 28, 2022)
• The MOSIS Service of the USC Information Sciences Institute and SkyWater Collaborate on Silicon IC Design Enablement and Manufacturing Service (Monday, November 28, 2022)
• Tachyum Successfully Runs LINPACK on FPGA With IEEE 754-2019 Compliant FPU (Monday, November 28, 2022)
• Truechip Announces First Customer Shipment of UCIe Verification IP (Monday, November 28, 2022)
• Faraday FPGA-Go-ASIC™ Succeeds in Penetrating the Market (Monday, November 21, 2022)
• Embrace the new age of ultra-high-definition multimedia with HDMI 2.0 Rx PHY IP Cores in 12FFC process technology with matching controller (Sunday, November 20, 2022)
• Truechip Announces First Customer Shipment of MIPI A-PHY Verification IP (Wednesday, November 16, 2022)
• Synopsys To Play A Key Role In Enabling Intel Foundry Services For US DOD Chip Program (Wednesday, November 16, 2022)
• StarFive Releases StarFive StarStudio IDE, which supports both Linux and Baremetal Development (Monday, November 14, 2022)
• Arasan announces MIPI CSI IP for FPGA supporting full C-PHY 2.0 speeds (Sunday, November 13, 2022)
• ZeroPoint Technologies can reduce data center energy consumption by 25% (Sunday, November 13, 2022)
• JEDEC Announces Publication of the SPD5118 Hub and Serial Presence Detect Device and the DDR5 SPD Contents Specifications (Sunday, November 13, 2022)
• Marvell Announces Innovative CXL Development Platform for Multi-Host Memory Pooling (Sunday, November 13, 2022)
• Cryogenic CMOS design enabled by Semiwise (Thursday, November 10, 2022)
• ShortLink AB and Dolphin Design partner to create a highly energy-efficient Sub-GHz ASIC design platform (Thursday, November 10, 2022)
• DDR5/DDR4/LPDDR5 Combo PHY IP Cores which is Silicon Proven in 12FFC with Matching Controller IP Cores is available for license to accelerate your Memory Interfacing Speeds (Tuesday, November 8, 2022)
• Chiplet Interconnect Technology Heads Toward Commercialization (Monday, November 7, 2022)
• Weebit Nano receives from SkyWater Technology the first silicon wafers it manufactured with embedded Weebit ReRAM (Monday, November 7, 2022)
• Arasan announces MIPI DSI IP for FPGA supporting full C-PHY 2.0 speeds (Monday, November 7, 2022)
• eMemory Receives 2022 TSMC OIP Partner of the Year Award for Embedded Memory IP (Sunday, November 6, 2022)
• NSITEXE develops "DR4100" General Purpose Accelerator for SoC (Thursday, November 3, 2022)
• Silicon Creations Named 2022 TSMC OIP Partner of the Year for Analog and Mixed-Signal IP (Wednesday, November 2, 2022)
• Bitech Technologies Reports Completion of Its FPGA design and the Launch of Its ASIC Initiatives for Bitcoin Mining (Tuesday, November 1, 2022)
• MIPI DSI and CSI Controllers IP Cores, for your High-Resolution Cameras, Display and Consumer Products, is available for immediate licensing (Sunday, October 30, 2022)
• Floadia Announces MTP IP without extra Mask Available on 55nm (Sunday, October 30, 2022)
• Weebit Nano successfully qualifies its ReRAM module (Wednesday, October 26, 2022)
• Cadence Integrity 3D-IC Platform Certified for TSMC 3DFabric Offerings (Wednesday, October 26, 2022)
• Cadence's New Flow Automates Custom/Analog Design Migration on TSMC Advanced Technologies (Wednesday, October 26, 2022)
• Cadence Digital and Custom/Analog Design Flows Achieve Certification for TSMC's Latest N4P and N3E Processes (Tuesday, October 25, 2022)