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Design Platform News
Synopsys Advances Silicon Lifecycle Management to Accelerate Data Transport and Significantly Reduce Test Time
(Monday, September 26, 2022)
Siemens automates 2.5D and 3D IC design-for-test with new Tessent Multi die solution
(Sunday, September 25, 2022)
CXL Spec Grows, Absorbs Others to Collate Ecosystem
(Sunday, September 25, 2022)
Split manufacturing for trustworthy electronics
(Wednesday, September 21, 2022)
Agile Analog launches new Digital Standard Cell Library
(Tuesday, September 20, 2022)
Synopsys Unveils Industry's First Unified Emulation and Prototyping System Addressing Verification Requirements Across the Chip Development Cycle
(Monday, September 19, 2022)
QuantWare awarded subsidy from Quantum Delta NL for €1.1M project to develop the use of novel materials in superconducting quantum processors
(Thursday, September 15, 2022)
Tachyum Enters QA Testing for Prodigy Universal Processor with New EDA Supplier
(Wednesday, September 14, 2022)
NIST and Google to Create New Supply of Chips for Researchers and Tech Startups
(Wednesday, September 14, 2022)
VeriSilicon Announces the One-Stop VeriHealth Chip Design Platform for Smart Healthcare Applications
(Tuesday, September 13, 2022)
Spreading the Quantum Knowledge
(Monday, September 12, 2022)
Brite Semiconductor Provides USB IP Total Solution
(Thursday, September 8, 2022)
Making chip design easy
(Monday, September 5, 2022)
Alphawave Adopts Diakopto's PrimeX™ as Top-Level EM/IR Signoff Methodology for 5nm and 3nm Technologies
(Monday, September 5, 2022)
Sondrel complements its Architecting the Future IP platforms with pre-packaged supply chains for reduced risk
(Monday, September 5, 2022)
Sonical partners with Dolphin Design to build the future of hearables
(Sunday, September 4, 2022)
USB Promoter Group Announces USB4® Version 2.0
(Thursday, September 1, 2022)
Siemens introduces Questa Verification IP solution support for the new CXL 3.0 protocol
(Monday, August 29, 2022)
SiMa.ai Achieves First Silicon Success with Synopsys Solutions, Launching the Industry's Most Power-Efficient MLSoC Platform for the Embedded Edge
(Monday, August 29, 2022)
Semico Research Concludes proteanTecs Deep Data Analytics Gives SoC Manufacturers a Six-Month Time-to-Market Advantage with Significant Savings
(Sunday, August 28, 2022)
CXL™ Consortium and JEDEC® Sign MOU Agreement to Advance DRAM and Persistent Memory Technology
(Wednesday, August 24, 2022)
Augment your Peripheral slot's performance with the Low Power and High Throughput PCIe 4.0 PHY IP Cores in 12FFC with matching PCIe 4.0 Controller IP Cores
(Sunday, August 21, 2022)
Diakopto Unveils PrimeX™ - Revolutionary EDA Solution for Top-Hierarchy Power Grid and Signal Net EM/IR
(Sunday, August 21, 2022)
JEDEC Updates Universal Flash Storage (UFS) and Supporting Memory Interface Standard
(Wednesday, August 17, 2022)
Efinix Low Power, Small Footprint FPGA Selected for SPRESENSE Development Platform
(Tuesday, August 16, 2022)
Truechip Announces First Customer Shipment of CXL 3 Verification IP and CXL Switch Model
(Thursday, August 11, 2022)
Arasan refreshes its Total USB IP Solution with its next generation of USB 2.0 PHY IP
(Wednesday, August 10, 2022)
Siemens selected by Microsoft for Rapid Assured Microelectronics Prototypes (RAMP) Program
(Tuesday, August 9, 2022)
Space Codesign Systems joins Siemens Digital Industries Software Solution Partner Program as a Software and Technology Partner
(Sunday, August 7, 2022)
Enhance your SD Card experience by integrating SD 4.1 UHS-II PHY IP Core to achieve Ultra High Speeds
(Sunday, August 7, 2022)
Cadence Accelerates Hyperscale SoC Design with Industry's First Verification IP and System VIP for CXL 3.0
(Thursday, August 4, 2022)
Cadence Library Characterization Solution Accelerates Delivery and Enhances Quality of Arm Memory Products
(Wednesday, August 3, 2022)
UCIe™ (Universal Chiplet Interconnect Express™) Consortium Announces Incorporation and New Board Members; Open for Membership
(Tuesday, August 2, 2022)
CXL Consortium Releases Compute Express Link 3.0 Specification to Expand Fabric Capabilities and Management
(Tuesday, August 2, 2022)
Accellera Announces Proposed Working Group to Explore Clock Domain Crossing Standard
(Tuesday, August 2, 2022)
Mobiveil and Avery Design Systems Extend Partnership to Accelerate Design and Verification of NVMe 2.0-Enabled SSD Development
(Monday, August 1, 2022)
CXL Consortium and OpenCAPI Consortium Sign Letter of Intent to Transfer OpenCAPI Specifications to CXL
(Monday, August 1, 2022)
Avery Design Announces CXL 3.0 VIP
(Monday, August 1, 2022)
Avery Design Systems Verification IP Helps Solid State Storage Controller Startup Validate its Designs and Get to Market Faster
(Sunday, July 31, 2022)
Faraday Unveiled FPGA-Go-ASIC Prototyping Platform to Accelerate FPGA-to-ASIC Conversion
(Wednesday, July 27, 2022)
MIPI UniPro v2.0 Doubles Peak Data Rate and Delivers Greater Throughput and Reduced Latency for Flash Memory Storage Applications
(Tuesday, July 26, 2022)
CFX announces commercial availability of anti-fuse OTP technology on 55nm CIS process
(Sunday, July 24, 2022)
Vidatronic Expands FinFET Portfolio with 7 nm to 4 nm FlexGUARD™ and Power Quencher® Intellectual Properties (IPs) Available for Licensing
(Monday, July 18, 2022)
In-house software team provides Sondrel with a key advantage for its turnkey ASIC service of turning concept into silicon
(Monday, July 18, 2022)
MIPI RFFE Master & Slave Controller IP Cores to control your complex RF-Front End Interfaces
(Sunday, July 17, 2022)
10Gbps!The fastest LPDDR5/5X IP deliver production !
(Sunday, July 17, 2022)
Siemens' Calibre platform expands early design verification solutions
(Tuesday, July 12, 2022)
Dutch Startup on the Way to Make Quantum Photonic Processors Real
(Monday, July 11, 2022)
Truechip Introduces Automation Products - NoC Verification and NoC Performance - for Revolutionizing the Verification Spectrum
(Monday, July 11, 2022)
Siemens' state-of-the-art Symphony Pro platform expands mixed signal IC verification capabilities
(Sunday, July 10, 2022)
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