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Design Platform and Service News

• Avery Continues to Drive CXL Adoption with New Virtual Platform Features in Support of Version 3.0 (Monday, October 24, 2022)
• Rambus Delivers PCIe 6.0 Interface Subsystem for High-Performance Data Center and AI SoCs (Monday, October 24, 2022)
• Cadence Joins Intel Foundry Services USMAG Alliance to Accelerate Chip Design Development (Monday, October 24, 2022)
• Nextera Video and Adeas ST 2110 and NMOS FPGA Cores Receive Latest JT-NM Tested Badges (Sunday, October 23, 2022)
• Marvell Announces Industry's Most Comprehensive 3nm Data Infrastructure IP Portfolio (Wednesday, October 19, 2022)
• SmartDV Achieves ISO 9001:2015 Certification (Tuesday, October 18, 2022)
• USB-IF Announces Publication of New USB4® Specification to Enable USB 80Gbps Performance (Tuesday, October 18, 2022)
• EnSilica looks to acquisitions, expands Bristol design centre (Monday, October 17, 2022)
• Arasan Partners with Testmetrix on its 4.5 GSPS C-PHY / D-PHY HDK and Compliance Test Platform (Monday, October 17, 2022)
• eInfochips Partners with Taoglas to Offer RF Design Services to Add Wireless Connectivity to Products (Sunday, October 16, 2022)
• MOSCHIP joins TSMC Design Center Alliance (Sunday, October 16, 2022)
• Brite Semiconductor Provides MIPI IP Total Solution (Thursday, October 13, 2022)
• Weebit Nano advances its ReRAM selector development to fit embedded & discrete applications (Wednesday, October 12, 2022)
• proteanTecs Edge™ Applications Now Available on the Advantest ACS Solution Store (Wednesday, October 12, 2022)
• New Cadence Certus Delivers Up to 10X Faster Concurrent Full-Chip Optimization and Signoff (Tuesday, October 11, 2022)
• Cadence and Google Cloud Collaborate to Advance the Electronic System and Semiconductor Design Ecosystem (Tuesday, October 11, 2022)
• DCD-SEMI introduces multiprotocol combo: HDLC, UART, SPI... with bigger FIFO and... (Monday, October 10, 2022)
• SEMI ESD Alliance Adds Axiomise to Member Roster (Monday, October 10, 2022)
• Introducing PCIe 4.0 PHY IP Cores in 7nm for a reliable, Low area and High-Speed Interface Peripheral slot for all your High-End Devices (Sunday, October 9, 2022)
• Perforce Delivers Enhanced Support for Test Automation in Latest Helix ALM Release (Tuesday, October 4, 2022)
• Synopsys Unveils Breakthrough Golden Signoff ECO Solution, Delivering 10x Productivity Improvement (Tuesday, October 4, 2022)
• Nobel prize awarded for quantum entanglement (Monday, October 3, 2022)
• EuroHPC JU Selects 6 Sites Across the EU for Quantum Computers (Monday, October 3, 2022)
• Synopsys Expands Code Sight Standard Edition with IntelliJ Support (Monday, October 3, 2022)
• Samsung Foundry Certifies Cadence Voltus-XFi Custom Power Integrity Solution for 5LPE Process Technology (Monday, October 3, 2022)
• Synopsys Unified Platform Tackles Verification Requirements (Sunday, October 2, 2022)
• SEMIFIVE Announces New 5nm HPC SoC Platform (Sunday, October 2, 2022)
• Siemens' Calibre platform now certified for Samsung's advanced 3nm process technology (Sunday, October 2, 2022)
• Introducing superfast serial interfacing with JESD204B Tx - Rx PHY IP Cores in 12nm, 28nm and 40nm for all type of ADC/DAC and ASIC/FPGA connections (Sunday, October 2, 2022)
• Intel Tackles Next-gen Computing with Quantum and Neuromorphic Innovations (Thursday, September 29, 2022)
• Vidatronic Unveils OmniPOWER™ Distributed Power Systems Available for Licensing in FinFET Technologies (Thursday, September 29, 2022)
• S2C Releases Neuro™ - Advanced Prototype Resource Management Software (Wednesday, September 28, 2022)
• Valens Semiconductor Collaborates with Intel to Boost Automotive MIPI A-PHY Implementations (Tuesday, September 27, 2022)
• European plugfest for MIPI I3C spec (Monday, September 26, 2022)
• Synopsys Advances Silicon Lifecycle Management to Accelerate Data Transport and Significantly Reduce Test Time (Monday, September 26, 2022)
• Siemens automates 2.5D and 3D IC design-for-test with new Tessent Multi die solution (Sunday, September 25, 2022)
• CXL Spec Grows, Absorbs Others to Collate Ecosystem (Sunday, September 25, 2022)
• Split manufacturing for trustworthy electronics (Wednesday, September 21, 2022)
• Agile Analog launches new Digital Standard Cell Library (Tuesday, September 20, 2022)
• Synopsys Unveils Industry's First Unified Emulation and Prototyping System Addressing Verification Requirements Across the Chip Development Cycle (Monday, September 19, 2022)
• QuantWare awarded subsidy from Quantum Delta NL for €1.1M project to develop the use of novel materials in superconducting quantum processors (Thursday, September 15, 2022)
• Tachyum Enters QA Testing for Prodigy Universal Processor with New EDA Supplier (Wednesday, September 14, 2022)
• NIST and Google to Create New Supply of Chips for Researchers and Tech Startups (Wednesday, September 14, 2022)
• VeriSilicon Announces the One-Stop VeriHealth Chip Design Platform for Smart Healthcare Applications (Tuesday, September 13, 2022)
• Spreading the Quantum Knowledge (Monday, September 12, 2022)
• Brite Semiconductor Provides USB IP Total Solution (Thursday, September 8, 2022)
• Making chip design easy (Monday, September 5, 2022)
• Alphawave Adopts Diakopto's PrimeX™ as Top-Level EM/IR Signoff Methodology for 5nm and 3nm Technologies (Monday, September 5, 2022)
• Sondrel complements its Architecting the Future IP platforms with pre-packaged supply chains for reduced risk (Monday, September 5, 2022)
• Sonical partners with Dolphin Design to build the future of hearables (Sunday, September 4, 2022)