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• Breker Verification Systems Unveils System Coherency Synthesis TrekApp Building on Its Successful Cache Coherency Test Solution (Sunday, December 5, 2021)
• What is Sensor Fusion? (Sunday, December 5, 2021)
• Synopsys Extends Industry Leadership as Customers Surpass 500 Tapeouts Using Flagship Fusion Compiler Solution (Wednesday, December 1, 2021)
• Samsung Foundry Adopts New Tempus SPICE-Accurate Aging Analysis for High-Reliability Applications (Wednesday, November 17, 2021)
• Synopsys 3DIC Compiler Qualified for Samsung Foundry's Multi-Die Integration Flow, Accelerating 2.5D and 3D Designs (Tuesday, November 16, 2021)
• Siemens extends support of multiple IC design solutions for Samsung Foundry's latest process technologies (Tuesday, November 16, 2021)
• Cadence Characterization Suite Enables Samsung Foundry to Get to Market Faster (Tuesday, November 16, 2021)
• Arteris IP Helps Automate System-on-Chip Semiconductor Design Traceability with Harmony Trace Design Data (Monday, November 15, 2021)
• Floadia Announces eNVM of 150 degree C retention on HHGrace 180BCD (Sunday, November 14, 2021)
• Xilinx Launches Alveo U55C, Its Most Powerful Accelerator Card Ever, Purpose-Built for HPC and Big Data Workloads (Sunday, November 14, 2021)
• Synopsys' PrimeShield Recognized by 2021 World Electronics Achievement Awards (Tuesday, November 9, 2021)
• Diakopto's ParagonX Platform Selected by The Six Semi for High-Speed Memory PHYs (Monday, November 8, 2021)
• Corigine Brings Prototyping And Emulation Acceleration To The Desktop With MimicTurbo GT Card (Sunday, November 7, 2021)
• Sondrel develops Performance Verification Environment to fast-track ASIC creation (Tuesday, November 2, 2021)
• Tessolve Joins GlobalFoundries' Design Enablement Network Program as a Design Partner to Bring Advanced Design Solutions to Accelerate Customer Product Development (Tuesday, November 2, 2021)
• Silicon Creations Named 2021 TSMC Partner of the Year for Analog / Mixed-Signal IP (Tuesday, November 2, 2021)
• proteanTecs UCT Supports TSMC 3nm Process Technology to Accelerate Lifecycle Health Monitoring (Tuesday, November 2, 2021)
• Siemens Collaborates with TSMC on Design Tool Certifications for Advanced Technologies (Sunday, October 31, 2021)
• Siemens collaborates with TSMC on design tool certifications for TSMC's advanced technologies and other industry milestones (Tuesday, October 26, 2021)
• Cadence Integrity 3D-IC Platform Supports TSMC 3DFabric Technologies for Advanced Multi-Chiplet Designs (Tuesday, October 26, 2021)
• JEDEC Publishes Update to DDR5 SDRAM Standard Used in High-Performance Computing Applications (Tuesday, October 26, 2021)
• Siemens collaborates with TSMC on design tool certifications (Tuesday, October 26, 2021)
• SD 5.1/eMMC 5.1 Host and Device Controllers with Matching PHYs for all kind of Portable Memory Storage Devices, making it easy to integrate a wide range of Applications in your products (Tuesday, October 26, 2021)
• Analog Bits to Present Papers, Demo of N5 Working Silicon, and Roadmap on IPs for TSMC N4 and N3 Processes (Monday, October 25, 2021)
• QuickLogic Announces First eFPGA IP From Australis IP Generator on UMC 22nm Process (Monday, October 25, 2021)
• Agile Analog broadens analogue IP portfolio (Monday, October 25, 2021)
• Siemens accelerates IP validation by 1,000X at Arm using ML-powered Solido Variation Designer on AWS Graviton2 (Wednesday, October 20, 2021)
• Cadence Digital and Custom/Analog Flows Achieve the Latest TSMC N3 and N4 Certifications (Wednesday, October 20, 2021)
• Synopsys Expands Strategic Technology Collaboration with TSMC to Extend 3D-System Integration Solutions for Next-Generation High-Performance Computing Designs (Tuesday, October 19, 2021)
• Synopsys Digital and Custom Design Platforms Achieve Certification for TSMC N3 Process (Tuesday, October 19, 2021)
• Imperas Models for Arm Processors now available in TESSY by Razorcat (Sunday, October 17, 2021)
• MosChip Announces Multi-Protocol Long Range 8G SerDes PHY in 28nm (Monday, October 11, 2021)
• Thalia's IP reuse platform joins Cadence Connections EDA Program (Sunday, October 10, 2021)
• Marvell Extends Data Infrastructure Leadership with TSMC 3nm Platform (Tuesday, October 5, 2021)
• Siemens introduces mPower power integrity solution for analog, digital and mixed-signal IC designs (Monday, September 27, 2021)
• Synopsys Achieves AIM Photonics Certification (Sunday, September 26, 2021)
• SiPearl opens design centre in Grenoble, looks for 50 engineers (Sunday, September 26, 2021)
• Cadence Accelerates Development of Mobile, Automotive and Hyperscale Systems with the Helium Virtual and Hybrid Studio (Wednesday, September 22, 2021)
• Samsung Foundry Certifies Synopsys PrimeLib Unified Library Characterization and Validation Solution at 5nm, 4nm and 3nm Process Nodes (Tuesday, September 21, 2021)
• Codasip Opens UK Design Center led by Simon Bewick (Monday, September 20, 2021)
• Cadence Collaborates with GlobalFoundries to Qualify Pegasus Verification System for 12LP/12LP+ and 22FDX™ Technologies (Tuesday, September 14, 2021)
• Siemens' Aprisa place-and-route solution now certified for GlobalFoundries' 22FDX platform (Tuesday, September 14, 2021)
• SmartDV Provides Broad Portfolio of Memory Modeling, Design and Verification Solutions (Monday, September 13, 2021)
• Synopsys PrimeSim Reliability Analysis Solution Accelerates Design of Hyper-Convergent ICs for Mission-Critical Applications (Sunday, September 12, 2021)
• EnSilica opens new design centre, starts recruitment drive (Tuesday, September 7, 2021)
• Cadence and Samsung Accelerate 3nm Mixed-Signal Silicon (Tuesday, September 7, 2021)
• VisualSim Cloud brings popular System-Level Modeling Solution to the Browser (Monday, September 6, 2021)
• EPFL launches quantum computing and technology centre (Monday, August 30, 2021)
• Photonic Chips for Fault-Tolerance Quantum Computing (Monday, August 30, 2021)
• eTopus Selects Diakopto's ParagonX Platform for Ultra-High Speed SerDes IP (Monday, August 23, 2021)