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• Thalia successfully completes 20th 22nm analog IP reuse engagement (Wednesday, March 3, 2021)
• Synopsys Announces Euclide to Accelerate Design and Verification Productivity (Tuesday, March 2, 2021)
• Achronix and Mobiveil Announce Partnership to Deliver High-Speed Controller IP and FPGA Engineering Services (Tuesday, March 2, 2021)
• Synopsys Delivers Breakthrough Performance with New ZeBu Empower Emulation System for Hardware-Software Power Verification (Tuesday, February 23, 2021)
• Synopsys Receives Customers' Choice Award for Paper Presented at TSMC 2020 Open Innovation Platform Ecosystem Forum (Monday, February 8, 2021)
• Pulsic Delivers Real-Time, Accurate, Layout Previews to Analog Circuits Designers with the new Animate Preview (Wednesday, February 3, 2021)
• Mirabilis Design integrates Fast Functional Processors into VisualSim Architect to close the software design, development and validation loop (Tuesday, January 26, 2021)
• HDL Design House Partners with Marketing Platform AnySilicon (Tuesday, January 26, 2021)
• Powerful FPGA Design Creation and Simulation IDE Adds VHDL-2019 Support & OSVVM Enhancements (Tuesday, January 19, 2021)
• Sondrel Selects Synopsys Fusion Design and Verification Platforms to Displace Legacy Design Tools (Monday, January 18, 2021)
• Sofics and Hardent join Mixel's MIPI ecosystem to provide designers a complete MIPI solution (Tuesday, December 15, 2020)
• UVM Reference Implementation Aligned with IEEE 1800.2-2020 Standard (Tuesday, December 15, 2020)
• The DDR5 Revolution: Promise & Challenges Ahead (Thursday, December 10, 2020)
• Renesas Strengthens IP License Portfolio with IP Utilities to Facilitate Device Development (Wednesday, December 9, 2020)
• SmartDV Announces New Line of Design IP Controllers for High-Speed Communications (Tuesday, December 8, 2020)
• Mentor joins Nano 2022 R&D program to foster innovation in semiconductor design and verification (Wednesday, November 18, 2020)
• Faraday's 22nm Fundamental IP Adopted for Intelligent IoT Devices (Wednesday, November 11, 2020)
• Vidatronic Achieves up to 10X Speedup Using the Cadence Spectre X Simulator (Wednesday, November 11, 2020)
• Graphcore leverages multiple Mentor technologies for its massive, second-generation AI platform (Monday, November 9, 2020)
• Avery Design Debuts QEMU Virtual Host to SystemVerilog PCIe VIP HW-SW Co-simulation Solution for Pre-silicon System-level Simulation of NVMe SSD and PCIe Designs (Monday, November 9, 2020)
• Aldec Introduces Hardware Assisted RTL Simulation Acceleration for Microchip FPGA Designs (Monday, November 2, 2020)
• Cadence Custom/AMS Flow Certified for the Samsung Foundry 3nm Advanced Process Technology for Early Design Starts (Wednesday, October 28, 2020)
• Synopsys and Samsung Release Certified 3nm Gate-All-Around AMS Design Reference Flow for Early Design Starts (Tuesday, October 27, 2020)
• Samsung Foundry Adopts Real Intent Meridian CDC for Clock Domain Crossing Sign-off (Tuesday, October 27, 2020)
• Codasip Announces a New Design Center in France (Monday, October 19, 2020)
• Synopsys to Enable New Levels of Insight into SoC Designs and Systems with Industry's First Silicon Lifecycle Management Platform (Monday, October 12, 2020)
• New Cadence Clarity 3D Transient Solver Delivers Up to 10X Faster System-Level EMI Simulation (Monday, October 12, 2020)
• Cadence Brings Verification IP to the Chip Level with New System VIP Solution (Monday, October 12, 2020)
• Cadence Announces Complete DDR5/LPDDR5 IP Solution for TSMC N5 Process Technology (Wednesday, October 7, 2020)
• Intento Design Expands Analog Automation with IDX-PVT, Eliminating the Need for Design-by-Verification (Wednesday, October 7, 2020)
• SmartDV Unveils SmartConf Testbench Generator (Tuesday, October 6, 2020)
• Efinix® Announces Availability of Reconfigurable Acceleration Platform (Monday, October 5, 2020)
• Efabless Extends Partnerships for Rapid Development Solution of Custom ICs (Wednesday, September 30, 2020)
• Moortec's In-Chip Sensing Fabric Enables Deeply Embedded Monitoring of Dynamic Conditions for Picocom's Baseband SoC for 5G Small Cells (Tuesday, September 29, 2020)
• New Neoverse Platforms Take on the Cloud, HPC, and the Edge (Monday, September 28, 2020)
• Efabless Expands support for Cloud-based Design Platform (Sunday, September 27, 2020)
• Analog Bits Announces Foundation Analog IP Availability on GLOBALFOUNDRIES 12LP FinFET Platform (Wednesday, September 23, 2020)
• Spectral Design & Test Inc. Announces 3rd Generation 45RFSOI Low Power SRAM Targeted at the 5G Mobile Device SoC Market (Tuesday, September 22, 2020)
• SmartDV Delivers First-to-Market MIPI A-PHY v1.0 Verification IP (Monday, September 21, 2020)
• Arteris IP FlexNoC & Resilience Package Support SemiDrive ISO 26262-Compliant Chip Production (Monday, September 21, 2020)
• Lattice Shrinks Design Footprint and Cost, Boosts Reliability in Embedded Systems with Single Wire Aggregation IP Solution (Wednesday, September 9, 2020)
• Analog Bits at TSMC OIP – A Complete On-Die Clock Subsystem for PCIe Gen 5 (Tuesday, September 8, 2020)
• Synopsys Introduces the Industry's First Unified Electronic and Photonic Design Platform (Tuesday, September 8, 2020)
• Blue Cheetah Technology Catalyzes Chiplet Ecosystem (Tuesday, September 8, 2020)
• Thalia and Dolphin Design announce partnership to transform analog IP re-use economics and to accelerate time to market (Sunday, September 6, 2020)
• Cadence IC Packaging Reference Flow Certified for the Latest TSMC Advanced Packaging Solutions (Tuesday, August 25, 2020)
• Synopsys and TSMC Accelerate 2.5D/3DIC Designs with Chip-on-Wafer-on-Substrate and Integrated Fan-Out Certified Design Flows (Monday, August 24, 2020)
• Synopsys Collaborates with TSMC to Accelerate 3nm Innovation, Enabling Next-Generation SoC Design (Monday, August 24, 2020)
• Cadence Announces Availability of UltraLink D2D PHY IP on TSMC N7, N6 and N5 Processes (Monday, August 24, 2020)
• Moortec Provides In-Chip Sensing Fabrics on TSMC N6 Process Technology (Tuesday, August 18, 2020)