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• Renesas Strengthens IP License Portfolio with IP Utilities to Facilitate Device Development (Wednesday, December 9, 2020)
• SmartDV Announces New Line of Design IP Controllers for High-Speed Communications (Tuesday, December 8, 2020)
• Mentor joins Nano 2022 R&D program to foster innovation in semiconductor design and verification (Wednesday, November 18, 2020)
• Vidatronic Achieves up to 10X Speedup Using the Cadence Spectre X Simulator (Wednesday, November 11, 2020)
• Faraday's 22nm Fundamental IP Adopted for Intelligent IoT Devices (Wednesday, November 11, 2020)
• Avery Design Debuts QEMU Virtual Host to SystemVerilog PCIe VIP HW-SW Co-simulation Solution for Pre-silicon System-level Simulation of NVMe SSD and PCIe Designs (Monday, November 9, 2020)
• Graphcore leverages multiple Mentor technologies for its massive, second-generation AI platform (Monday, November 9, 2020)
• Aldec Introduces Hardware Assisted RTL Simulation Acceleration for Microchip FPGA Designs (Monday, November 2, 2020)
• Cadence Custom/AMS Flow Certified for the Samsung Foundry 3nm Advanced Process Technology for Early Design Starts (Wednesday, October 28, 2020)
• Samsung Foundry Adopts Real Intent Meridian CDC for Clock Domain Crossing Sign-off (Tuesday, October 27, 2020)
• Synopsys and Samsung Release Certified 3nm Gate-All-Around AMS Design Reference Flow for Early Design Starts (Tuesday, October 27, 2020)
• Codasip Announces a New Design Center in France (Monday, October 19, 2020)
• Cadence Brings Verification IP to the Chip Level with New System VIP Solution (Monday, October 12, 2020)
• New Cadence Clarity 3D Transient Solver Delivers Up to 10X Faster System-Level EMI Simulation (Monday, October 12, 2020)
• Synopsys to Enable New Levels of Insight into SoC Designs and Systems with Industry's First Silicon Lifecycle Management Platform (Monday, October 12, 2020)
• Intento Design Expands Analog Automation with IDX-PVT, Eliminating the Need for Design-by-Verification (Wednesday, October 7, 2020)
• Cadence Announces Complete DDR5/LPDDR5 IP Solution for TSMC N5 Process Technology (Wednesday, October 7, 2020)
• SmartDV Unveils SmartConf Testbench Generator (Tuesday, October 6, 2020)
• Efinix® Announces Availability of Reconfigurable Acceleration Platform (Monday, October 5, 2020)
• Efabless Extends Partnerships for Rapid Development Solution of Custom ICs (Wednesday, September 30, 2020)
• Moortec's In-Chip Sensing Fabric Enables Deeply Embedded Monitoring of Dynamic Conditions for Picocom's Baseband SoC for 5G Small Cells (Tuesday, September 29, 2020)
• New Neoverse Platforms Take on the Cloud, HPC, and the Edge (Monday, September 28, 2020)
• Efabless Expands support for Cloud-based Design Platform (Sunday, September 27, 2020)
• Analog Bits Announces Foundation Analog IP Availability on GLOBALFOUNDRIES 12LP FinFET Platform (Wednesday, September 23, 2020)
• Spectral Design & Test Inc. Announces 3rd Generation 45RFSOI Low Power SRAM Targeted at the 5G Mobile Device SoC Market (Tuesday, September 22, 2020)
• Arteris IP FlexNoC & Resilience Package Support SemiDrive ISO 26262-Compliant Chip Production (Monday, September 21, 2020)
• SmartDV Delivers First-to-Market MIPI A-PHY v1.0 Verification IP (Monday, September 21, 2020)
• Lattice Shrinks Design Footprint and Cost, Boosts Reliability in Embedded Systems with Single Wire Aggregation IP Solution (Wednesday, September 9, 2020)
• Blue Cheetah Technology Catalyzes Chiplet Ecosystem (Tuesday, September 8, 2020)
• Synopsys Introduces the Industry's First Unified Electronic and Photonic Design Platform (Tuesday, September 8, 2020)
• Analog Bits at TSMC OIP – A Complete On-Die Clock Subsystem for PCIe Gen 5 (Tuesday, September 8, 2020)
• Thalia and Dolphin Design announce partnership to transform analog IP re-use economics and to accelerate time to market (Sunday, September 6, 2020)
• Cadence IC Packaging Reference Flow Certified for the Latest TSMC Advanced Packaging Solutions (Tuesday, August 25, 2020)
• Cadence Announces Availability of UltraLink D2D PHY IP on TSMC N7, N6 and N5 Processes (Monday, August 24, 2020)
• Synopsys Collaborates with TSMC to Accelerate 3nm Innovation, Enabling Next-Generation SoC Design (Monday, August 24, 2020)
• Synopsys and TSMC Accelerate 2.5D/3DIC Designs with Chip-on-Wafer-on-Substrate and Integrated Fan-Out Certified Design Flows (Monday, August 24, 2020)
• NSITEXE Adopts Synopsys HAPS Prototyping to Validate Data Flow Processor IP (Tuesday, August 18, 2020)
• Moortec Provides In-Chip Sensing Fabrics on TSMC N6 Process Technology (Tuesday, August 18, 2020)
• S2C and Mirabilis Design Teamup to Deliver a Heterogeneous Solution for SoC Architecture Exploration and Verification (Monday, August 17, 2020)
• Nuvoton Accelerates the Development of its MCU Designs with the Cadence Palladium Z1 Enterprise Emulation Platform (Monday, August 17, 2020)
• SiFive Announces OpenFive, an Industry-Leading Custom Silicon Business Unit (Sunday, August 16, 2020)
• Synopsys Introduces Integrated Electric Vehicle Virtual Prototyping Solution (Wednesday, August 12, 2020)
• Truechip Announces Customer Shipment Of USB4 And eUSB Verification IPs (Sunday, August 9, 2020)
• Intento Design announces the launch of ID-Calibre, an ID-Substrate extension for behavioural TCAD simulation on a complete AMS chip (Wednesday, July 29, 2020)
• Marvell Unveils the Industry's Most Comprehensive Custom ASIC Offering (Monday, July 27, 2020)
• Cadence and UMC Certify mmWave Reference Flow on 28HPC+ Process for Advanced RF Designs (Wednesday, July 22, 2020)
• Carlos Mazure, EVP of Soitec and Chairman of the SOI Industry Consortium, Joins Silvaco Board of Directors (Wednesday, July 22, 2020)
• Alchip Technologies 7nm ASIC Capabilities Set Advanced Technology Pace (Tuesday, July 21, 2020)
• GLOBALFOUNDRIES Partners with Synopsys, Mentor, and Keysight on Interoperable Process Design Kit (iPDK) Support for 22FDX (Tuesday, July 21, 2020)
• CFI funding fuels new services for researchers from CMC and CNDN (Monday, July 20, 2020)