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Design Platform and Service News

• Synopsys unveils breakthrough in emulation performance (Monday, May 17, 2021)
• Thalia's AMALIA Technology Analyzer de-risks Analog IP reuse for major IP houses and IC manufacturers (Monday, May 17, 2021)
• Sondrel's latest reference IP platform enables ultra-powerful signal and data processing SoCs to be created faster for lower costs (Sunday, May 9, 2021)
• Synopsys Delivers Enhanced Memory Design Productivity to Nanya Technology (Tuesday, May 4, 2021)
• SmartDV Unveils Automation Tool Suite for Use with Its Extensive Verification IP Portfolio (Monday, May 3, 2021)
• Cadence collaborates with Arm to accelerate SoC development (Tuesday, April 27, 2021)
• "KI-PREDICT" – Intelligent process monitoring with on-sensor signal preprocessing (Tuesday, April 27, 2021)
• Astera Labs and Avery Design Partner on CXL 2.0 Verification for Smart Retimer Portfolio to Improve Performance in Data-Centric Applications (Tuesday, April 27, 2021)
• proteanTecs Joins Open Compute Project, Unveils UCT Monitoring System (Thursday, April 22, 2021)
• Siemens Place-and-route Solution Now Qualified on TSMC's N6 Technology (Thursday, April 22, 2021)
• Hardent Selected as Design Services Provider for New Xilinx Kria SOMs (Tuesday, April 20, 2021)
• Synopsys Introduces PrimeLib Unified Library Characterization and Validation Solution for Accelerated Access to Advanced Process Nodes (Tuesday, April 20, 2021)
• Synopsys Unleashes PrimeSim Continuum Solution to Accelerate the Design of Hyper-Convergent ICs for Memory, AI, Automotive and 5G Applications (Monday, April 19, 2021)
• Movellus Launches Maestro Intelligent Clock Network Platform for SoC Designs (Monday, April 19, 2021)
• Avery Design Debuts CXL 2.0 System-level VIP Simulation Solution (Wednesday, April 14, 2021)
• Semiconductor Energy Laboratory and Silvaco Jointly Develop SPICE Model of Oxide Semiconductor FETs (Tuesday, April 13, 2021)
• UK memory startup raises €1.5m, looks to imec (Tuesday, April 6, 2021)
• Siemens Emulation and Prototyping Tools Tackle SoC Design Challenges (Saturday, April 3, 2021)
• Truechip Adds New Customer Shipments Of Verification IPs For DDR, LPDDR And I3C v1.1 (Wednesday, March 31, 2021)
• Cadence Unveils Next-Generation Sigrity X for Up to 10X Faster System Analysis (Tuesday, March 16, 2021)
• Vtool Appoints EmergeTek as Cogita Sales Representative (Wednesday, March 10, 2021)
• Thalia successfully completes 20th 22nm analog IP reuse engagement (Wednesday, March 3, 2021)
• Achronix and Mobiveil Announce Partnership to Deliver High-Speed Controller IP and FPGA Engineering Services (Tuesday, March 2, 2021)
• Synopsys Announces Euclide to Accelerate Design and Verification Productivity (Tuesday, March 2, 2021)
• Synopsys Delivers Breakthrough Performance with New ZeBu Empower Emulation System for Hardware-Software Power Verification (Tuesday, February 23, 2021)
• Synopsys Receives Customers' Choice Award for Paper Presented at TSMC 2020 Open Innovation Platform Ecosystem Forum (Monday, February 8, 2021)
• Pulsic Delivers Real-Time, Accurate, Layout Previews to Analog Circuits Designers with the new Animate Preview (Wednesday, February 3, 2021)
• HDL Design House Partners with Marketing Platform AnySilicon (Tuesday, January 26, 2021)
• Mirabilis Design integrates Fast Functional Processors into VisualSim Architect to close the software design, development and validation loop (Tuesday, January 26, 2021)
• Powerful FPGA Design Creation and Simulation IDE Adds VHDL-2019 Support & OSVVM Enhancements (Tuesday, January 19, 2021)
• Sondrel Selects Synopsys Fusion Design and Verification Platforms to Displace Legacy Design Tools (Monday, January 18, 2021)
• UVM Reference Implementation Aligned with IEEE 1800.2-2020 Standard (Tuesday, December 15, 2020)
• Sofics and Hardent join Mixel's MIPI ecosystem to provide designers a complete MIPI solution (Tuesday, December 15, 2020)
• The DDR5 Revolution: Promise & Challenges Ahead (Thursday, December 10, 2020)
• Renesas Strengthens IP License Portfolio with IP Utilities to Facilitate Device Development (Wednesday, December 9, 2020)
• SmartDV Announces New Line of Design IP Controllers for High-Speed Communications (Tuesday, December 8, 2020)
• Mentor joins Nano 2022 R&D program to foster innovation in semiconductor design and verification (Wednesday, November 18, 2020)
• Vidatronic Achieves up to 10X Speedup Using the Cadence Spectre X Simulator (Wednesday, November 11, 2020)
• Faraday's 22nm Fundamental IP Adopted for Intelligent IoT Devices (Wednesday, November 11, 2020)
• Avery Design Debuts QEMU Virtual Host to SystemVerilog PCIe VIP HW-SW Co-simulation Solution for Pre-silicon System-level Simulation of NVMe SSD and PCIe Designs (Monday, November 9, 2020)
• Graphcore leverages multiple Mentor technologies for its massive, second-generation AI platform (Monday, November 9, 2020)
• Aldec Introduces Hardware Assisted RTL Simulation Acceleration for Microchip FPGA Designs (Monday, November 2, 2020)
• Cadence Custom/AMS Flow Certified for the Samsung Foundry 3nm Advanced Process Technology for Early Design Starts (Wednesday, October 28, 2020)
• Samsung Foundry Adopts Real Intent Meridian CDC for Clock Domain Crossing Sign-off (Tuesday, October 27, 2020)
• Synopsys and Samsung Release Certified 3nm Gate-All-Around AMS Design Reference Flow for Early Design Starts (Tuesday, October 27, 2020)
• Codasip Announces a New Design Center in France (Monday, October 19, 2020)
• Cadence Brings Verification IP to the Chip Level with New System VIP Solution (Monday, October 12, 2020)
• New Cadence Clarity 3D Transient Solver Delivers Up to 10X Faster System-Level EMI Simulation (Monday, October 12, 2020)
• Synopsys to Enable New Levels of Insight into SoC Designs and Systems with Industry's First Silicon Lifecycle Management Platform (Monday, October 12, 2020)
• Intento Design Expands Analog Automation with IDX-PVT, Eliminating the Need for Design-by-Verification (Wednesday, October 7, 2020)