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• D&R announces the opening of an IP Core Store to support Soft IP Cores sales to the Chinese market (Monday, December 2, 2019)
• Moortec's In-Chip Monitoring Subsystem Supports Uhnder in Groundbreaking Digital Automotive Radar-on-Chip (Sunday, December 1, 2019)
• SmartDV's Platform-Independent VIP Portfolio Ensures Seamless Coverage-Driven Verification Flow (Wednesday, November 20, 2019)
• EasyIC Design joins Arm Approved Design Partner Program (Monday, November 18, 2019)
• SmartDV to Exhibit at SemIsrael Expo, ICCAD China 2019 (Wednesday, November 6, 2019)
• Cadence Announces Tempus Power Integrity Solution for Signoff Timing-Aware IR Drop Analysis (Tuesday, November 5, 2019)
• Mentor boosts 64-bit Arm-based server platform by enabling Arm architecture support for Questa simulation tools (Monday, October 7, 2019)
• IC'Alps joins Arm Approved Design Partner program to better support customers with ASIC development (Monday, October 7, 2019)
• Dream Chip Technologies joined Samsung Foundry's Design Solution Partner (DSP) Program (Monday, October 7, 2019)
• HDL Design House Appoints Frank Werner as Worldwide Sales Director (Monday, September 30, 2019)
• SmartDV Adds Support for Verilator Open Source HDL Verilog Simulator (Monday, September 30, 2019)
• Gen-Z Physical Layer Specification 1.1 now available for download (Sunday, September 29, 2019)
• Veriest kick-starts Formal Verification methodology at Valens (Tuesday, September 17, 2019)
• SmartDV Announces Availability of Ethernet TSN Design IP (Monday, September 16, 2019)
• SmartDV to Demonstrate TileLink Verification IP for RISC-V Based Systems, Smart ViPDebug Protocol Debugger at DVCon India (Tuesday, September 10, 2019)
• sureCore Unveils Low Power Design Service (Monday, August 26, 2019)
• SmartDV to Exhibit at OpenPower Summit August 19-20 (Tuesday, August 13, 2019)
• Tessolve Highlights Test Engineering Practices, Participating At The ITC India 2019 As Platinum Sponsors (Tuesday, July 30, 2019)
• Cadence Delivers Portable Test and Stimulus Methodology and Library (Tuesday, July 16, 2019)
• Arm Flexible Access gives chip designers the freedom to experiment and test before they invest (Monday, July 15, 2019)
• Tower Semiconductor : TowerJazz, Cadence and Lumerical Deliver Silicon-Photonics and SiGe- Integrated PDK with a Complete Optical Transceiver Design Environment (Tuesday, July 9, 2019)
• Cadence Announces First-to-Market DisplayPort 2.0 Verification IP (Tuesday, June 25, 2019)
• Mentor's new Calibre Recon functionality methodically analyzes "early draft" IC designs for faster verification (Tuesday, May 28, 2019)
• Cadence Launches Protium X1, the First Scalable, Data Center-Optimized Enterprise Prototyping System for Early Software Development (Monday, May 27, 2019)
• Synopsys and Arm Extend Collaboration to Fusion Compiler to Accelerate Implementation of Arm's Next-Generation Client and Infrastructure Cores (Monday, May 13, 2019)
• eSilicon Tapes Out 7nm Combo PHY (HBM2/HBM2E/Low Latency) Test Chip (Wednesday, May 8, 2019)
• SmartDV Heads to ChipEx2019 in Israel with Extensive Design and Verification IP Portfolio (Monday, May 6, 2019)
• Synopsys Announces Industry's First DDR5 NVDIMM-P Verification IP for Next-generation Storage-class Memory Designs (Tuesday, April 30, 2019)
• Moortec Provide Embedded Monitoring Solutions for Arm's Neoverse N1 System Development Platform on TSMC 7nm Process Technology (Tuesday, April 30, 2019)
• Moortec To Showcase Its PVT Monitoring IP At TSMC 2019 Boston Technology Workshop (Monday, April 29, 2019)
• Moortec to Showcase its PVT Monitoring IP at TSMC 2019 Technology Symposium (Tuesday, April 16, 2019)
• SmartDV's DVCon China Exhibit to Showcase Extensive Verification IP Portfolio (Tuesday, April 9, 2019)
• Cadence Eyes System Analysis Market (Monday, April 1, 2019)
• UltraSoC demonstrates advanced multicore debug at Embedded World 2019 (Monday, February 25, 2019)
• SmartDV Unveils SimXL Portfolio of Synthesizable Transactors for Hardware Emulation, FPGA Prototyping Platforms (Wednesday, February 13, 2019)
• Sankalp Semiconductor to Exhibit & Participate at IESA Vision Summit 2019 (Monday, February 11, 2019)
• SmartDV Supports RISC-V Movement with TileLink Verification IP for RISC-V Based Systems (Tuesday, February 5, 2019)
• Silvacos FastSPICE Simulator Selected by Kodenshi for Sensor Device Design (Monday, December 3, 2018)
• MicroBT employs Moortec's 16nm Embedded Temperature Sensor in their HPC ASIC (Wednesday, November 28, 2018)
• New Mentor Symphony platform addresses nanometer-scale SoC mixed-signal verification challenges (Tuesday, November 6, 2018)
• Cadence Custom/AMS Flow Certified on Samsung 7LPP Process Technology (Tuesday, October 23, 2018)
• Synopsys FineSim SPICE Cuts Analog Simulation Time by 3X (Monday, October 22, 2018)
• ISG Positions L&T Technology Services as Global Leader in the First Ever Service Provider Ranking on Product, Process and Platform Engineering (Thursday, October 18, 2018)
• Agnisys at DVCON Europe 2018: Presenting End-to-End Solution for Specification to Design and Verification of the Hardware/Software Interface (Monday, October 15, 2018)
• Everest Group Positions L&T Technology Services as a global 'Leader' in Embedded System Engineering Services (Monday, October 8, 2018)
• sureCore Opens Low-Power SRAM IP Customization Service (Monday, September 24, 2018)
• Faraday ASIC Service Leverages Samsung FinFET Platform to Target Next-generation Applications (Monday, August 27, 2018)
• Cadence Palladium Z1 Enterprise Emulation Platform Enables GUC to Accelerate SoC Design (Monday, August 13, 2018)
• EASii IC (France) becomes Arm Approved Design Partner (Thursday, July 19, 2018)
• HDL Design House Greece Joins HETIA (Monday, July 16, 2018)