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Design Platform and Service News

• Synopsys Enables Tapeout Success for Early Adopters of Arm's Next Generation of Mobile IP (Monday, May 25, 2020)
• S2C Announces New Prodigy Cloud System for Next Generation SoC Prototyping (Wednesday, May 20, 2020)
• Cadence Delivers 10 New Verification IP Targeting Automotive, Hyperscale Data Center and Mobile Applications (Monday, May 18, 2020)
• SmartDV Ships First Design and Verification IP for MIPI RFFE v3.0 Specification (Monday, May 11, 2020)
• Faraday's SoCreative!V Platform Accelerates SoC Development in Edge Applications (Monday, May 4, 2020)
• Dolphin Design unveils its innovative Energy Efficient Platforms, complete turnkey solutions for competitive SoC designs (Sunday, May 3, 2020)
• Khronos Group Releases OpenCL 3.0 (Monday, April 27, 2020)
• Synopsys Introduces 3DIC Compiler, Industry's First Unified Platform to Accelerate Multi-die System Design and Integration (Monday, April 27, 2020)
• Mirabilis Design is making the standard training class on Model-based System Simulation and Electronic System-Level Design for free (Monday, April 6, 2020)
• Veriest International On-line Verification Meetup (Monday, March 30, 2020)
• SiFive Selects Synopsys Fusion Design Platform and Verification Continuum Platform to Enable Rapid SoC Design (Tuesday, March 24, 2020)
• InterMotion Technology boosts IP verification productivity for Lattice Semiconductor's CrossLink FPGA family using Aldec's Active-HDL (Monday, March 23, 2020)
• Faraday Delivers System-Level ESD Protection Service to Reduce ASIC Time-to-Market (Monday, March 16, 2020)
• Cadence Digital Full Flow Optimized to Deliver Improved Quality of Results with Up to 3X Faster Throughput (Monday, March 16, 2020)
• SiFive Launches Advanced Trace and Debug Portfolio, SiFive Insight (Monday, March 16, 2020)
• Synopsys Unveils RTL Architect To Accelerate Design Closure (Sunday, March 15, 2020)
• Synopsys Custom Design Platform Secures Full-flow Displacement of Legacy Design Tools at Alphawave (Monday, March 9, 2020)
• Faraday Announces Low-DPPM Solution for a Wide Range of ASIC Applications (Wednesday, March 4, 2020)
• UMC certifies Mentor product lines for its new 22nm ultra-low-power process technology (Wednesday, March 4, 2020)
• Defacto Announces STAR 8.0 and Provides a Unified "All-in-One" SoC Design Solution to Help Conciliating Between RTL, IP-XACT, UPF, SDC, and Physical Design Information (Tuesday, March 3, 2020)
• Veriest contributes to the verification of Nuvoton's Computing MCU devices (Tuesday, March 3, 2020)
• Gowin Semiconductor Adds Ubuntu Support to their Gowin EDA FPGA Software for Improved Artificial Intelligence and IoT Development Toolchain Integration (Wednesday, February 19, 2020)
• Synopsys' Fusion Compiler Adopted by AMD (Tuesday, February 18, 2020)
• SmartDV Offers New Design IP for DDR5 and LPDDR5 (Monday, February 17, 2020)
• UltraSoC collaborates with PDF Solutions to prevent in-life product failures using end-to-end analytics and advanced machine learning techniques (Wednesday, February 12, 2020)
• SmartDV Adds Support for MIPI I3C 1.1 Across Entire IP Portfolio (Tuesday, February 11, 2020)
• SmartDV Achieves Record Revenue in 2019 (Monday, February 3, 2020)
• Imagination Technologies expands with new design centre in Romania (Wednesday, January 15, 2020)
• Cadence Expands Collaboration with Broadcom for 5nm and 7nm Designs (Monday, January 13, 2020)
• NEC Selects Synopsys ZeBu Server 4 Emulation Solution for Super Computer Verification (Thursday, December 19, 2019)
• Codasip Studio and Codasip CodeSpace 8.2 available (Sunday, December 15, 2019)
• INSPECTOR™ diagnostic and debug platform passed the PCIe 4.0 compliance (Monday, December 9, 2019)
• NSITEXE Selects SmartDV TileLink Verification IP for RISC-V Based Applications (Monday, December 9, 2019)
• SmartDV's TileLink, Verilator VIP on Full Display at RISC-V Summit (Tuesday, December 3, 2019)
• D&R announces the opening of an IP Core Store to support Soft IP Cores sales to the Chinese market (Monday, December 2, 2019)
• Moortec's In-Chip Monitoring Subsystem Supports Uhnder in Groundbreaking Digital Automotive Radar-on-Chip (Sunday, December 1, 2019)
• SmartDV's Platform-Independent VIP Portfolio Ensures Seamless Coverage-Driven Verification Flow (Wednesday, November 20, 2019)
• EasyIC Design joins Arm Approved Design Partner Program (Monday, November 18, 2019)
• SmartDV to Exhibit at SemIsrael Expo, ICCAD China 2019 (Wednesday, November 6, 2019)
• Cadence Announces Tempus Power Integrity Solution for Signoff Timing-Aware IR Drop Analysis (Tuesday, November 5, 2019)
• Mentor boosts 64-bit Arm-based server platform by enabling Arm architecture support for Questa simulation tools (Monday, October 7, 2019)
• IC'Alps joins Arm Approved Design Partner program to better support customers with ASIC development (Monday, October 7, 2019)
• Dream Chip Technologies joined Samsung Foundry's Design Solution Partner (DSP) Program (Monday, October 7, 2019)
• HDL Design House Appoints Frank Werner as Worldwide Sales Director (Monday, September 30, 2019)
• SmartDV Adds Support for Verilator Open Source HDL Verilog Simulator (Monday, September 30, 2019)
• Gen-Z Physical Layer Specification 1.1 now available for download (Sunday, September 29, 2019)
• Veriest kick-starts Formal Verification methodology at Valens (Tuesday, September 17, 2019)
• SmartDV Announces Availability of Ethernet TSN Design IP (Monday, September 16, 2019)
• SmartDV to Demonstrate TileLink Verification IP for RISC-V Based Systems, Smart ViPDebug Protocol Debugger at DVCon India (Tuesday, September 10, 2019)
• sureCore Unveils Low Power Design Service (Monday, August 26, 2019)