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• Comcores JESD204D IP core confirming to the Revision D of the JESD204 standard released in Dec'2023 now available (Sunday, January 7, 2024)
• Creonic GmbH Joins the Science and Innovation Alliance Kaiserslautern (Sunday, January 7, 2024)
• OPENEDGES Achieves ISO9001: 2015 Certification, Proving IP Quality for its Customers (Sunday, January 7, 2024)
• DisplayPort v1.4 Tx PHY and Controller IP Cores which is Silicon proven in 12nm technology and also production proven is available for Worldwide instant licensing (Sunday, January 7, 2024)
• Faraday Collaborates in Arm Total Design to Provide Arm Neoverse CSS-based Design Services (Wednesday, January 3, 2024)
• M31 Successfully Validates 12nm USB4 PHY IP Empowering Next-Generation High-Speed Data Transmission (Tuesday, January 2, 2024)
• Ventana Microsystems Drives India's Chiplet Innovation in 2024 (Monday, January 1, 2024)
• Ventana Microsystems Drives India's Chiplet Innovation in 2024 (Monday, January 1, 2024)
• ELECTRA IC Marks a Decade of Design and Verification Excellence at CES 2024 (Monday, January 1, 2024)
• Accelerate Innovation: Harnessing the Speed of Tomorrow with PCIe Gen 4 PHY and Controller IP Cores (Monday, January 1, 2024)
• PCIe 6.0 moves closer to arriving in the market in 2024: Alphawave demonstrates interoperability (Thursday, December 28, 2023)
• U.K. Conference Accelerates Post-Quantum Cryptography Standards Review Process (Thursday, December 28, 2023)
• Rambus Advances Data Center Server Performance with Industry-First Gen4 DDR5 RCD (Wednesday, December 27, 2023)
• Europe Aims for Leadership Role in Quantum Computing (Monday, December 25, 2023)
• Quantum predictions for 2024 (Wednesday, December 20, 2023)
• Siemens collaborates with sureCore and Semiwise to pioneer quantum computing ready cryogenic semiconductor designs (Tuesday, December 19, 2023)
• World's first UCIe heterogeneous chiplet test chip (Sunday, December 17, 2023)
• Alphawave Semi Partners with Keysight to Deliver Industry Leading Expertise and Interoperability for a Complete PCIe 6.0 Subsystem Solution (Thursday, December 14, 2023)
• QC Design announces launch of fault-tolerance design automation tool Plaquette+ and first sale to QuiX Quantum (Wednesday, December 13, 2023)
• Imec's extremely scaled SOT-MRAM devices show record low switching energy and virtually unlimited endurance (Wednesday, December 13, 2023)
• Maximize uptime, capacity utilization, and energy efficiency with always-ready CFD models and data center digital twin technology (Tuesday, December 12, 2023)
• Alchip Unveils AI 3DIC Design and IP Platform (Tuesday, December 12, 2023)
• Continental and Synopsys Provide Vehicle Digital Twin Capabilities to Accelerate Software Development (Monday, December 11, 2023)
• EnSilica enters strategic partners with design and custom module developer IndesmaTech (Sunday, December 10, 2023)
• 12-bit 2GS/s high-speed ADC IP Core with Seamless Integration, Ultimate Precision is ready for Immediate Licensing (Sunday, December 10, 2023)
• Layer transfer tech comes to high volume chiplet, 2nm manufacturing (Thursday, December 7, 2023)
• Ceva Wins Product of the Year Award at Prestigious EE Awards Asia Event (Wednesday, December 6, 2023)
• Siemens' new Calibre DesignEnhancer boosts Samsung Foundry design quality and speeds time to market (Wednesday, December 6, 2023)
• Applied Materials and CEA-Leti Unveil Joint Lab For Rapidly Growing Specialty Chip Markets (Monday, December 4, 2023)
• Tenstorrent Strengthens Presence in Asia with Rapidus Partnership (Monday, December 4, 2023)
• Agile Analog partners with sureCore on CryoCMOS Innovate UK project (Monday, December 4, 2023)
• Quantum effect technology breakthrough in analogue circuit design (Sunday, December 3, 2023)
• ADTechnology is accelerating its performance and targeting infrastructure markets by joining Arm Total Design. (Sunday, December 3, 2023)
• Cadence Signoff Solutions Empower Samsung Foundry's Breakthrough Success on 5G Networking SoC Design (Wednesday, November 29, 2023)
• Omni Design Technologies Announces Expanded Silicon IP Solutions on Multiple TSMC Processes (Tuesday, November 28, 2023)
• M31 Completes Validation of 7nm ONFI 5.1 I/O IP - Targeting for the Global AI Big Data Storage Market (Tuesday, November 28, 2023)
• Manufacturers Anticipate Completion of NVIDIA's HBM3e Verification by 1Q24; HBM4 Expected to Launch in 2026, Says TrendForce (Tuesday, November 28, 2023)
• Quantum Effect Technology Breakthrough in Analog Circuit Design (Tuesday, November 28, 2023)
• Siemens revolutionizes engineering simulation with HEEDS AI Simulation Predictor and Simcenter Reduced Order Modeling (Monday, November 27, 2023)
• Bridging the Talent Gap in Flanders' Semiconductor Industry (Monday, November 27, 2023)
• Production Proven USB 3.2 Gen1/Gen2 IP Cores to ensure a seamless throughput for Next-Gen SoCs available for Immediate licensing (Monday, November 27, 2023)
• Tenstorrent Gains Momentum in Asia With Rapidus Partnership (Sunday, November 26, 2023)
• BrainChip Announces Dr. Tony Lewis as the New Chief Technology Officer (Wednesday, November 22, 2023)
• LeWiz Open Source LVDS Transceiver Design (Wednesday, November 22, 2023)
• Alchip Unveils Industry's First Automotive ASIC Design Platform (Tuesday, November 21, 2023)
• Weebit Nano's ReRAM IP achieves high temperature qualification in SkyWater Technology's S130 process (Sunday, November 19, 2023)
• Faraday Unveils Enhanced Gigabit Ethernet PHY on UMCÂ’s 28HPC+ Process (Wednesday, November 15, 2023)
• Thalia's AMALIA (23.4a) qualified on Siemens AFS for increased analog design migration flexibility (Wednesday, November 15, 2023)
• Movellus Introduces Aeonic Insight™ Product Line for On-die Telemetry (Monday, November 13, 2023)
• CXL Consortium Announces Compute Express Link 3.1 Specification Release (Monday, November 13, 2023)