Search News

RISC-V News

• Semidynamics Announces Cervell™ All-in-One RISC-V NPU Delivering Scalable AI Compute for Edge and Datacenter Applications (Monday, May 5, 2025)
• Codasip launches complete exploration platform to accelerate CHERI adoption (Monday, April 28, 2025)
• Baya Systems, Imagination Technologies and Andes Technology to Present on Heterogeneous Compute Architectures at Andes RISC-V CON Silicon Valley (Sunday, April 27, 2025)
• FPGA prototyping harnessed for RISC-V processor cores (Thursday, April 24, 2025)
• S2C and Andes Technology Announce FPGA-Based Prototyping Partnership to Accelerate Advanced RISC-V SoC Development (Wednesday, April 23, 2025)
• New Breakthroughs in China's RISC-V Chip Industry (Thursday, April 17, 2025)
• Andes Technology Celebrates 20 Years with New Logo and Headquarters Expansion (Wednesday, April 16, 2025)
• Defacto Technologies Automates Front-End SoC Integration for Large RISC-V Designs (Sunday, April 13, 2025)
• Ubuntu developer images now available for OrangePi RV2: a low-cost RISC-V SBC (Wednesday, April 9, 2025)
• Will RISC-V reduce auto MCU's future risk? (Sunday, April 6, 2025)
• 2025 RISC-V CON: Andes Technology Celebrates 20 Years, Bringing Together Innovators, Engineers, and Ecosystem Leaders (Thursday, April 3, 2025)
• Will RISC-V reduce auto MCU's future risk? (Tuesday, April 1, 2025)
• LDRA Updates Tools to Automate Worst-Case Execution Time Analysis for RISC-V (Friday, March 28, 2025)
• Hong Kong investment arm backs Chinese RISC-V start-up StarFive in tech push (Thursday, March 20, 2025)
• China Bets on Homegrown Chip Tech With RISC-V Push (Sunday, March 16, 2025)
• Codasip selected to design a high-end RISC-V processor for the EU-funded DARE project (Wednesday, March 5, 2025)
• Infineon brings RISC-V to the automotive industry and is first to announce an automotive RISC-V microcontroller family (Wednesday, March 5, 2025)
• Infineon, Synopsys to show virtual prototype of first automotive RISC-V microcontroller (Wednesday, March 5, 2025)
• €240m DARE project for AI RISC-V chiplets (Wednesday, March 5, 2025)
• Quintauris launches the first RISC-V profile for today's real-time automotive applications (Tuesday, March 4, 2025)
• Semidynamics' Aliado SDK Accelerates AI Development for RISC-V with Seamless ONNX Integration (Monday, March 3, 2025)
• Baya Systems and Semidynamics Collaborate to Accelerate RISC-V System-on-Chip Development (Tuesday, February 25, 2025)
• Jim Keller joins ex-Intel chip designers in RISC-V startup focused on breakthrough CPUs (Tuesday, February 25, 2025)
• Andes Technology and proteanTecs Partner to Bring Performance and Reliability Monitoring to RISC-V Cores (Monday, February 24, 2025)
• Cortus MINERVA Out-of-Order 4GHz 64-bit RISC-V Processor Platform targets automotive applications (Sunday, February 23, 2025)
• Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification (Thursday, February 20, 2025)
• Ex-Intel team raise $21.5m to pursue RISC-V for AI (Wednesday, February 19, 2025)
• Why RISC-V is a viable option for safety-critical applications (Thursday, February 13, 2025)
• RISC-V in Space Workshop 2025 in Gothenburg (Monday, February 3, 2025)
• CHERI Protects Memory at the Hardware Level (Monday, February 3, 2025)
• Codasip and RED Semiconductor Sign Memorandum of Understanding to Develop AI Acceleration Technologies (Wednesday, January 29, 2025)
• Codasip, RED Semiconductor team for RISC-V AI acceleration (Monday, January 27, 2025)
• Support added in RISC-V IP for automotive high safety and security applications (Monday, January 20, 2025)
• RISC-V in AI and HPC Part 2: Per Aspera Ad Astra? (Monday, January 13, 2025)
• RISC-V in AI and HPC Part 2: Per Aspera Ad Astra? (Monday, January 13, 2025)
• RISC-V in AI and HPC Part 2: Per Aspera Ad Astra? (Monday, January 13, 2025)
• RISC-V in AI and HPC Part 2: Per Aspera Ad Astra? (Monday, January 13, 2025)
• Imagination quits RISC-V CPU business to focus on GPUs and AI (Wednesday, January 8, 2025)
• RISC-V in AI and HPC Part 1: Per Aspera Ad Astra? (Sunday, January 5, 2025)
• RISC-V Made Nice Software Progress In 2024 While Interesting Hardware Still Rare (Tuesday, December 31, 2024)
• Arm vs. RISC-V in 2025: Which Architecture Will Lead the Way? (Monday, December 23, 2024)
• Andes Technology Partners with ProvenRun to Strengthen RISC-V Trusted Execution Environment (Tuesday, December 17, 2024)
• Jmem Tek and Andes Technology Partner on the World' s First Quantum-Secure RISC-V Chip (Tuesday, December 10, 2024)
• UPMEM selects Semidynamics RISC-V AI IP for Large Language Model Application (Sunday, December 8, 2024)
• Imagination PowerVR Driver Being Extended To Work On RISC-V (Wednesday, December 4, 2024)
• SiFive Empowers AI at Scale with RISC-V Innovation (Tuesday, December 3, 2024)
• HighTec C/C++ Compiler Suite Supports Andes' ISO 26262 Certified RISC-V IP for Automotive Safety and Security Applications (Wednesday, November 27, 2024)
• Andes Technology Collaborates with Lauterbach to Deliver RISC-V Trace Solution (Monday, November 25, 2024)
• Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy (Wednesday, November 20, 2024)
• SC24 Observations: China, Politics, RISC-V and CXL (Wednesday, November 20, 2024)