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RISC-V News

• RISC-V in AI and HPC Part 2: Per Aspera Ad Astra? (Monday, January 13, 2025)
• RISC-V in AI and HPC Part 2: Per Aspera Ad Astra? (Monday, January 13, 2025)
• RISC-V in AI and HPC Part 2: Per Aspera Ad Astra? (Monday, January 13, 2025)
• RISC-V in AI and HPC Part 2: Per Aspera Ad Astra? (Monday, January 13, 2025)
• Imagination quits RISC-V CPU business to focus on GPUs and AI (Wednesday, January 8, 2025)
• RISC-V in AI and HPC Part 1: Per Aspera Ad Astra? (Sunday, January 5, 2025)
• RISC-V Made Nice Software Progress In 2024 While Interesting Hardware Still Rare (Tuesday, December 31, 2024)
• Arm vs. RISC-V in 2025: Which Architecture Will Lead the Way? (Monday, December 23, 2024)
• Andes Technology Partners with ProvenRun to Strengthen RISC-V Trusted Execution Environment (Tuesday, December 17, 2024)
• Jmem Tek and Andes Technology Partner on the World' s First Quantum-Secure RISC-V Chip (Tuesday, December 10, 2024)
• UPMEM selects Semidynamics RISC-V AI IP for Large Language Model Application (Sunday, December 8, 2024)
• Imagination PowerVR Driver Being Extended To Work On RISC-V (Wednesday, December 4, 2024)
• SiFive Empowers AI at Scale with RISC-V Innovation (Tuesday, December 3, 2024)
• HighTec C/C++ Compiler Suite Supports Andes' ISO 26262 Certified RISC-V IP for Automotive Safety and Security Applications (Wednesday, November 27, 2024)
• Andes Technology Collaborates with Lauterbach to Deliver RISC-V Trace Solution (Monday, November 25, 2024)
• Universal AI RISC-V processor does it all - CPU, GPU, DSP, FPGA (Wednesday, November 20, 2024)
• Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M (Wednesday, November 20, 2024)
• SC24 Observations: China, Politics, RISC-V and CXL (Wednesday, November 20, 2024)
• Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy (Wednesday, November 20, 2024)
• Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC (Sunday, November 17, 2024)
• RISC-V for HPC at SC24 (Friday, November 15, 2024)
• What RISC-V Means for the Future of Chip Development (Tuesday, November 12, 2024)
• CHERI builds global chip security alliance (Monday, November 11, 2024)
• lowRISC and SCI Semiconductor Partner to Create First CHERIoT Commercial Tapeout (Monday, November 11, 2024)
• Arteris and MIPS Partner on High-Performance RISC-V SoCs for Automotive, Datacenter and Edge AI (Monday, November 11, 2024)
• Tenstorrent to Build Japanese Engineering Talent with US-Based AI and RISC-V Training (Monday, November 4, 2024)
• 4 Highlights From the RISC-V Summit North America (Monday, October 28, 2024)
• SCI Semiconductor announces Global-First CHERI enabled devices and Early Access Program (Wednesday, October 23, 2024)
• RISC-V reaches milestone with RVA23 profile ratification (Tuesday, October 22, 2024)
• First CHERI RISC-V embedded chip and Early Access Programme (Tuesday, October 22, 2024)
• RISC-V Announces Ratification of the RVA23 Profile Standard (Monday, October 21, 2024)
• Fractile Licenses Andes Technology's RISC-V Vector Processor as It Builds Radical New Chip to Accelerate AI Inference (Monday, October 21, 2024)
• DeepComputing and Andes Technology Partner to Develop the WorldÂ’s First RISC-V AI PC with 7nm QiLai SoC, Featuring Ubuntu Desktop (Monday, October 21, 2024)
• DeepComputing and Andes Technology Partner to Develop the World's First RISC-V AI PC with 7nm QiLai SoC, Featuring Ubuntu Desktop (Monday, October 21, 2024)
• Andes Technology Unveils the D45-SE RISC-V Processor Targeting ASIL-D Certification (Monday, October 21, 2024)
• SiFive HiFive Premier P550 Development Boards Now Shipping (Sunday, October 20, 2024)
• Codasip enables secure Linux by donating CHERI RISC-V SDK to the CHERI Alliance (Sunday, October 20, 2024)
• Arteris and SiFive Deliver Pre-verified Solution for the Datacenter Market (Sunday, October 20, 2024)
• Andes Announces the AndesCore™ AX66 supporting RVA23, Multi-cluster, Hypervisor and Android (Sunday, October 20, 2024)
• Andes Announces the AndesCore™ 46-Series Family and the 3rd generation Vector Processor AX46MPV with Matrix Extension (Sunday, October 20, 2024)
• The role of RISC-V in the European Processor Initiative - Interview with Roger Espasa (Thursday, October 17, 2024)
• Codasip unveils versatile automotive-grade embedded RISC-V core (Monday, October 14, 2024)
• Kernkonzept and Lauterbach Make Virtualized RISC-V Systems Possible (Sunday, October 13, 2024)
• Intel Architects Start RISC-V Business with AheadComputing (Wednesday, October 9, 2024)
• LDRA Announces Extended Support for RISC-V High Assurance Software Quality Tool Suite to Accelerate On-Target Testing of Critical Embedded Applications (Wednesday, October 9, 2024)
• Debug and Trace Support for Synopsys ARC-V Processor IP (Tuesday, October 8, 2024)
• Samsung ports Tizen OS to RISC-V (Saturday, October 5, 2024)
• Flexible RISC-V processor offers prospect of low-cost smart objects (Sunday, September 29, 2024)
• Codeplay Brings RISC-V Support to the oneAPI Construction Kit (Sunday, September 22, 2024)
• VyperCore plans 5nm RISC-V server chip and card (Sunday, September 22, 2024)