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RISC-V News

• Arteris Selected by Esperanto Technologies to Integrate RISC-V Processors for High-Performance AI and Machine Learning Solutions (Monday, June 10, 2024)
• Andes Technology Announces the Annual ANDES RISC-V CON on June 11th at the DoubleTree San Jose Hotel (Thursday, June 6, 2024)
• Andes RISC-V CON: Deep Dive into Automotive, AI Application Processors and Security Trend (Thursday, June 6, 2024)
• Codasip introduces best-in-class RISC-V core for power-efficient applications (Monday, June 3, 2024)
• Rain AI Unveils Andes Technology as Its RISC-V Partner (Sunday, June 2, 2024)
• Andes Technology Announced the QiLai SoC and the Voyager Development Board (Wednesday, May 29, 2024)
• World's first RISC-V multi-mode LTE chipset for 450MHz (Tuesday, May 28, 2024)
• SEALSQ RISC-V Chips Adoption is Predicted to Get AI Boost Making it a Viable Competitor to Traditional GPUs (Sunday, May 26, 2024)
• RISC-V adoption predicted to get AI boost ? forecast shows 50% growth every year until 2030 for the open-standard ISA (Sunday, May 26, 2024)
• RISC-V adoption predicted to get AI boost - forecast shows 50% growth every year until 2030 for the open-standard ISA (Monday, May 20, 2024)
• Andes Technology and Arteris Partner To Accelerate RISC-V SoC Adoption (Monday, May 20, 2024)
• RISC-V adoption will be accelerated by AI, according to new research (Sunday, May 19, 2024)
• RISC-V Chip Combines CPU, GPU, and NPU Into One Core (Tuesday, May 14, 2024)
• Frontgrade Gaisler Leads the Way in RISC-V Processor Development for Space Applications (Monday, May 13, 2024)
• Andes, HiRain, and HPMicro Join Hands to Build RISC-V AUTOSAR Software Ecosystem (Monday, May 13, 2024)
• lowRISC Deploys Real Intent Ascent Lint, Meridian CDC, & Meridian RDC for OpenTitan Project (Sunday, May 12, 2024)
• X-Silicon Announces a NEW Low-Power Open-Standard Vulkan-Enabled C-GPU™ - a RISC-V Vector CPU Infused with GPU ISA and AI/ML acceleration in a Single Processor Core (Wednesday, May 8, 2024)
• Radiation-Tolerant PolarFire® SoC FPGAs Offer Low Power, Zero Configuration Upsets, RISC-V Architecture for Space Applications (Wednesday, May 1, 2024)
• Radiation-Tolerant RISC-V FPGA for Linux in space (Tuesday, April 30, 2024)
• Industry's First General-Purpose 32-bit RISC-V MCU Core Expands Design Freedom (Tuesday, April 23, 2024)
• Controversial former Arm China CEO founds RISC-V chip startup (Sunday, April 21, 2024)
• Brazil and Europe sign innovative project with RISC-V technology for HPC (Sunday, April 14, 2024)
• VISC: The New Coprocessing RISC-V Architecture for AI Efficiency (Friday, April 12, 2024)
• Winners of the Embedded World awards (Tuesday, April 9, 2024)
• SiFive Unveils the HiFive Premier P550, the First Commercially Available Out-of-Order RISC-V Development Board (Monday, April 8, 2024)
• TASKING presents compiler toolset for RISC-V in safety- and security-critical automotive applications (Monday, April 8, 2024)
• RISC-V International Achieves Milestone with Ratification of 40 Specifications in Two Years (Sunday, April 7, 2024)
• MIPS Expands RISC-V Ecosystem Support to to Enable Early Software Development for Multi-threaded Cores (Sunday, April 7, 2024)
• Imagination's new Catapult CPU is driving RISC-V device adoption (Sunday, April 7, 2024)
• IAR, Nuclei, and MachineWare Join Forces To Speed Up Innovation in RISC-V ASIL Compliant Automotive Solution (Sunday, April 7, 2024)
• New RISC-V microprocessor can run CPU, GPU, and NPU workloads simultaneously (Wednesday, April 3, 2024)
• Red Semiconductor announces VISC extension to RISC-V (Monday, April 1, 2024)
• First general-purpose 32-bit RISC-V MCUs with internally developed CPU core (Thursday, March 28, 2024)
• Renesas Introduces Industry's First General-Purpose 32-bit RISC-V MCUs with Internally Developed CPU Core (Monday, March 25, 2024)
• Achronix FPGAs Add Support for Bluespec's Linux-capable RISC-V Soft Processors to Enable Scalable Processing (Monday, March 25, 2024)
• Alibaba's research arm promises server-class RISC-V processor due this year (Tuesday, March 19, 2024)
• embedded world 2024: Codasip demonstrates CHERI memory protection (Wednesday, March 13, 2024)
• Andes Technology: Cultivating Academic Collaboration for Over a Decade with Sustainable Spirit (Monday, March 11, 2024)
• Free configurator puts the power of full core customisation into hands of customers (Sunday, March 10, 2024)
• Nuclei System Technology collaborates with Siemens to deliver RISC-V Processor Trace Encoder solution (Tuesday, March 5, 2024)
• Imsys develops RISC-V core, looks to AI in space (Tuesday, March 5, 2024)
• Semidynamics puts the power of full core customisation into hands of customers (Monday, March 4, 2024)
• Scaleway launches its RISC-V servers in the cloud, a world first and a firm commitment to technological independence (Sunday, March 3, 2024)
• French cloud Scaleway starts renting Alibaba's RISC-V SoC (Sunday, March 3, 2024)
• Microchip's Low-Cost PolarFire® SoC Discovery Kit Makes RISC-V and FPGA Design More Accessible for a Wider Range of Embedded Engineers (Monday, February 26, 2024)
• Andes and MachineWare Collaborate on Early RISC-V Software Development for AndesCore™ AX45MPV (Monday, February 26, 2024)
• Microchip Launches PolarFire RISC-V and FPGA Development Board (Sunday, February 25, 2024)
• Andes Technology and MetaSilicon Collaborate to Build the World's First Automotive-Grade CMOS Image Sensor Product Using RISC-V IP SoC (Wednesday, February 21, 2024)
• Tessolve's Ambitious Leap: Championing RISC-V's Global Surge from India (Tuesday, February 20, 2024)
• Tenstorrent Selects Blue Cheetah Chiplet Interconnect IP For Its AI and RISC-V Solutions (Monday, February 5, 2024)