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RISC-V News

• BellSoft releases Liberica JDK 21 for RISC-V with support (Wednesday, January 31, 2024)
• Navigating the RISC-V Revolution in Europe (Tuesday, January 30, 2024)
• Frontgrade Gaisler and RISC-V's Space Journey (Wednesday, January 17, 2024)
• YorChip, Inc. announces its first Chiplet for Edge AI applications with IP licensed from Semidynamics, the leader in RISC-V IP based in Barcelona (Tuesday, January 16, 2024)
• Video: Leveraging the RISC-V efficient trace (E-Trace) standard (Monday, January 15, 2024)
• Digital Blocks AMBA Multi-Channel DMA Controller IP Core Family Extends Leadership with releases for core DMA Engines in RISC-V® & ARM® Systems and Peripherals to Memory Applications (Sunday, January 14, 2024)
• Edge-side AI audio processor now features RISC-V AndesCore D25F (Thursday, January 11, 2024)
• CEO interview: MIPS' Sameer Wasson on a RISC-V reboot (Tuesday, January 9, 2024)
• Andes Technology and Spacetouch Collaborate to Unveil High-Tech Edge-Side AI Audio Processor Featuring the Powerful RISC-V AndesCore™ D25F (Monday, January 8, 2024)
• The SHD Group Has Released a Complimentary Version of the 2024 RISC-V Market Analysis Report Containing Current Market Data and Future Projections (Sunday, January 7, 2024)
• China Is All In on a RISC-V Future (Sunday, January 7, 2024)
• Andes Announces General Availability of the New RISC-V Out-Of-Order Superscalar Multicore Processor, the AndesCore™ AX65 (Thursday, January 4, 2024)
• MIPS Inc. (San Jose, Calif.) has recruited Drew Barbier and Brad Burgess to its leadership team, both formerly with RISC-V pioneer SiFive Inc. (Wednesday, January 3, 2024)
• MIPS recruits former senior SiFive execs to boost RISC-V play (Wednesday, January 3, 2024)
• MIPS Welcomes New Executives as Part of Company's Growth and Expansion (Tuesday, January 2, 2024)
• MIPS snags top SiFive brains to amp up RISC-V business (Tuesday, January 2, 2024)
• 3 trends for 2024: AI drives more edge intelligence, RISC-V, & chiplets (Monday, January 1, 2024)
• Five Leading Semiconductor Industry Players Incorporate New Company, Quintauris, to Drive RISC-V Ecosystem Forward (Thursday, December 21, 2023)
• BSC presents Sargantana, the new generation of the first open-source chips designed in Spain (Thursday, December 14, 2023)
• GigaDevice partners with SEGGER on Embedded Studio for RISC-V (Wednesday, December 13, 2023)
• Free development tools for Gigadevice RISC-V microcontrollers (Tuesday, December 12, 2023)
• Andes Awards Imperas 2023 Partner of the Year (Monday, December 11, 2023)
• Renesas Champions the RISC-V Cause With Its Own 32-bit RISC-V CPU (Tuesday, December 5, 2023)
• Keeping It 100: RISC-V Reality Check (Monday, December 4, 2023)
• Canonical joins the RISC-V Software Ecosystem (RISE) (Sunday, December 3, 2023)
• Renesas Unveils the First Generation of Own 32-bit RISC-V CPU Core Ahead of Competition (Wednesday, November 29, 2023)
• Amidst export restrictions, RISC-V continues to advance (Tuesday, November 28, 2023)
• New RISC-V processors address demand for open source and performance (Monday, November 20, 2023)
• Ventana Micro Systems Unveils Second Generation Veyron Family RISC-V Processor, Paving the Way for Data Center-Class Performance (Sunday, November 19, 2023)
• Andes Technology Partners with WITTENSTEIN high integrity systems (WHIS) to Build Safety-Critical Solutions with RISC-V Processors (Monday, November 13, 2023)
• RISC-V Pioneer SiFive Takes Stock, Realigns, Moves Forward (Wednesday, November 8, 2023)
• RISC-V International Marks Banner Year for RISC-V Adoption, Technical Momentum, and Community Engagement (Tuesday, November 7, 2023)
• China Deploys Massive RISC-V Server in Commercial Cloud (Tuesday, November 7, 2023)
• Ventana and Imagination Partner to Deliver World's Highest Performance RISC-V CPU & GPU Solutions (Tuesday, November 7, 2023)
• OpenHW Group Announces CORE-V CVA6 Platform Project for RISC-V Software Development & Testing (Tuesday, November 7, 2023)
• Ventana Introduces Veyron V2 - World's Highest Performance Data Center-Class RISC-V Processor and Platform (Tuesday, November 7, 2023)
• Ubilite Licenses RISC-V Application Processor IP Core from CAST (Monday, November 6, 2023)
• Synopsys Expands Its ARC Processor IP Portfolio with New RISC-V Family (Monday, November 6, 2023)
• Hyperion Core Joins RISC-V International as a Strategic Member (Sunday, November 5, 2023)
• TASKING, Andes, and MachineWare Team Up to Facilitate Rapid Development of RISC-V ASIL Compliant Automotive Silicon (Sunday, November 5, 2023)
• Ansys medini Accelerates Andes' Development of Automotive-Grade IP (Thursday, November 2, 2023)
• Imperas RISC-V Solutions for Developers - Accelerating RISC-V (Wednesday, November 1, 2023)
• Sophgo Licenses SiFive RISC-V Processor Cores to Drive High-Performance AI Computing Innovation (Wednesday, November 1, 2023)
• Semidynamics and Arteris Partner To Accelerate AI RISC-V System-on-Chip Development (Wednesday, November 1, 2023)
• Axiomise Heads to Silicon Valley Next Week for RISC-V Summit North America (Tuesday, October 31, 2023)
• Tenstorrent Teams with Imperas to Provide Model of the Tenstorrent Ascalon RISC-V Core (Monday, October 30, 2023)
• lowRISC Announces New OpenTitan Project Partner, zeroRISC (Monday, October 30, 2023)
• Codasip delivers processor security to actively prevent the most common cyberattacks (Monday, October 30, 2023)
• RISC-V Releases Abound Ahead of 2023 RISC-V Summit (Friday, October 27, 2023)
• SiFive lays off 20% of staff, re-aligns business (Tuesday, October 24, 2023)