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RISC-V News

• RISC-V Chip Combines CPU, GPU, and NPU Into One Core (Tuesday, May 14, 2024)
• Andes, HiRain, and HPMicro Join Hands to Build RISC-V AUTOSAR Software Ecosystem (Monday, May 13, 2024)
• Frontgrade Gaisler Leads the Way in RISC-V Processor Development for Space Applications (Monday, May 13, 2024)
• lowRISC Deploys Real Intent Ascent Lint, Meridian CDC, & Meridian RDC for OpenTitan Project (Sunday, May 12, 2024)
• X-Silicon Announces a NEW Low-Power Open-Standard Vulkan-Enabled C-GPU™ - a RISC-V Vector CPU Infused with GPU ISA and AI/ML acceleration in a Single Processor Core (Wednesday, May 8, 2024)
• Radiation-Tolerant PolarFire® SoC FPGAs Offer Low Power, Zero Configuration Upsets, RISC-V Architecture for Space Applications (Wednesday, May 1, 2024)
• Radiation-Tolerant RISC-V FPGA for Linux in space (Tuesday, April 30, 2024)
• Industry's First General-Purpose 32-bit RISC-V MCU Core Expands Design Freedom (Tuesday, April 23, 2024)
• Controversial former Arm China CEO founds RISC-V chip startup (Sunday, April 21, 2024)
• Brazil and Europe sign innovative project with RISC-V technology for HPC (Sunday, April 14, 2024)
• VISC: The New Coprocessing RISC-V Architecture for AI Efficiency (Friday, April 12, 2024)
• Winners of the Embedded World awards (Tuesday, April 9, 2024)
• TASKING presents compiler toolset for RISC-V in safety- and security-critical automotive applications (Monday, April 8, 2024)
• SiFive Unveils the HiFive Premier P550, the First Commercially Available Out-of-Order RISC-V Development Board (Monday, April 8, 2024)
• IAR, Nuclei, and MachineWare Join Forces To Speed Up Innovation in RISC-V ASIL Compliant Automotive Solution (Sunday, April 7, 2024)
• Imagination's new Catapult CPU is driving RISC-V device adoption (Sunday, April 7, 2024)
• MIPS Expands RISC-V Ecosystem Support to to Enable Early Software Development for Multi-threaded Cores (Sunday, April 7, 2024)
• RISC-V International Achieves Milestone with Ratification of 40 Specifications in Two Years (Sunday, April 7, 2024)
• New RISC-V microprocessor can run CPU, GPU, and NPU workloads simultaneously (Wednesday, April 3, 2024)
• Red Semiconductor announces VISC extension to RISC-V (Monday, April 1, 2024)
• First general-purpose 32-bit RISC-V MCUs with internally developed CPU core (Thursday, March 28, 2024)
• Achronix FPGAs Add Support for Bluespec's Linux-capable RISC-V Soft Processors to Enable Scalable Processing (Monday, March 25, 2024)
• Renesas Introduces Industry's First General-Purpose 32-bit RISC-V MCUs with Internally Developed CPU Core (Monday, March 25, 2024)
• Alibaba's research arm promises server-class RISC-V processor due this year (Tuesday, March 19, 2024)
• embedded world 2024: Codasip demonstrates CHERI memory protection (Wednesday, March 13, 2024)
• Andes Technology: Cultivating Academic Collaboration for Over a Decade with Sustainable Spirit (Monday, March 11, 2024)
• Free configurator puts the power of full core customisation into hands of customers (Sunday, March 10, 2024)
• Imsys develops RISC-V core, looks to AI in space (Tuesday, March 5, 2024)
• Nuclei System Technology collaborates with Siemens to deliver RISC-V Processor Trace Encoder solution (Tuesday, March 5, 2024)
• Semidynamics puts the power of full core customisation into hands of customers (Monday, March 4, 2024)
• French cloud Scaleway starts renting Alibaba's RISC-V SoC (Sunday, March 3, 2024)
• Scaleway launches its RISC-V servers in the cloud, a world first and a firm commitment to technological independence (Sunday, March 3, 2024)
• Andes and MachineWare Collaborate on Early RISC-V Software Development for AndesCore™ AX45MPV (Monday, February 26, 2024)
• Microchip's Low-Cost PolarFire® SoC Discovery Kit Makes RISC-V and FPGA Design More Accessible for a Wider Range of Embedded Engineers (Monday, February 26, 2024)
• Microchip Launches PolarFire RISC-V and FPGA Development Board (Sunday, February 25, 2024)
• Andes Technology and MetaSilicon Collaborate to Build the World's First Automotive-Grade CMOS Image Sensor Product Using RISC-V IP SoC (Wednesday, February 21, 2024)
• Tessolve's Ambitious Leap: Championing RISC-V's Global Surge from India (Tuesday, February 20, 2024)
• Tenstorrent Selects Blue Cheetah Chiplet Interconnect IP For Its AI and RISC-V Solutions (Monday, February 5, 2024)
• BellSoft releases Liberica JDK 21 for RISC-V with support (Wednesday, January 31, 2024)
• Navigating the RISC-V Revolution in Europe (Tuesday, January 30, 2024)
• Frontgrade Gaisler and RISC-V's Space Journey (Wednesday, January 17, 2024)
• YorChip, Inc. announces its first Chiplet for Edge AI applications with IP licensed from Semidynamics, the leader in RISC-V IP based in Barcelona (Tuesday, January 16, 2024)
• Video: Leveraging the RISC-V efficient trace (E-Trace) standard (Monday, January 15, 2024)
• Digital Blocks AMBA Multi-Channel DMA Controller IP Core Family Extends Leadership with releases for core DMA Engines in RISC-V® & ARM® Systems and Peripherals to Memory Applications (Sunday, January 14, 2024)
• Edge-side AI audio processor now features RISC-V AndesCore D25F (Thursday, January 11, 2024)
• CEO interview: MIPS' Sameer Wasson on a RISC-V reboot (Tuesday, January 9, 2024)
• Andes Technology and Spacetouch Collaborate to Unveil High-Tech Edge-Side AI Audio Processor Featuring the Powerful RISC-V AndesCore™ D25F (Monday, January 8, 2024)
• China Is All In on a RISC-V Future (Sunday, January 7, 2024)
• The SHD Group Has Released a Complimentary Version of the 2024 RISC-V Market Analysis Report Containing Current Market Data and Future Projections (Sunday, January 7, 2024)
• Andes Announces General Availability of the New RISC-V Out-Of-Order Superscalar Multicore Processor, the AndesCore™ AX65 (Thursday, January 4, 2024)