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RISC-V News

• Leading Semiconductor Industry Players Join Forces to Accelerate RISC-V (Monday, August 7, 2023)
• Terapines ZCC Toolchain Fully Supports Andes RISC-V Processors (Sunday, July 30, 2023)
• Esperanto Merging HPC and ML in Upcoming RISC-V Processor (Sunday, July 30, 2023)
• RISC-V Moving Toward Open Server Specification (Sunday, July 23, 2023)
• Semidynamics announces fully customisable, 4-way, Atrevido 423 RISC-V core for big data applications (Wednesday, July 19, 2023)
• How China is Building an Open National Chip Plan Around RISC-V (Tuesday, July 18, 2023)
• Startups Help RISC-V Reshape Computer Architecture (Monday, July 17, 2023)
• DAC 2023: RISC-V is not in the future, it's now (Sunday, July 16, 2023)
• Imperas details verification of automotive AI RISC-V vector processor IP (Monday, July 10, 2023)
• StarFive and Youyeetoo jointly delivered the official metal case for VisionFive 2 (Sunday, July 2, 2023)
• Tiempo Secure's new TESIC RISC-V IP successfully passes SERMA CC EAL5+ security assessment tests (Sunday, July 2, 2023)
• Bluespec Launches New MCUX RISC-V Processor That Enables Developers to Implement Custom Instructions and Add Accelerators (Wednesday, June 28, 2023)
• The European Project Creating Extensible, Energy-Efficient RISC-V CPUs (Tuesday, June 27, 2023)
• Andes Technology Unveils the Annual Andes RISC-V CON, Scheduled for June 27th at the San Jose Airport DoubleTree Hotel (Monday, June 26, 2023)
• Bluespec Launches New MCUX RISC-V Processor That Enables Developers to Implement Custom Instructions and Add Accelerators (Monday, June 26, 2023)
• Codasip partners with SmartDV to accelerate chip design projects (Wednesday, June 21, 2023)
• Jim Keller on AI, RISC-V, Tenstorrent's Move to Edge IP (Sunday, June 11, 2023)
• RISC-V Summit Europe 2023 ended in Barcelona but the #riscv revolution has only just begun (Friday, June 9, 2023)
• Green Hills Software adds support for production-ready RTOS and tools to Imagination Technologies' RISC-V CPUs (Tuesday, June 6, 2023)
• Imperas at the RISC-V Summit Europe, June 5-9 2023 (Sunday, June 4, 2023)
• Agile Analog launches first complete RISC-V analog IP subsystem at RISC-V Summit Europe (Sunday, June 4, 2023)
• Andes Technology Showcases Pioneering RISC-V CPU IP Solutions at RISC-V Summit Europe (Sunday, June 4, 2023)
• Consortium's Move Will Boost RISC-V Ecosystem, Thankfully (Sunday, June 4, 2023)
• Complete RISC-V analog IP subsystem targets IoT (Sunday, June 4, 2023)
• Axiomise Launches Next-Generation formalISA App for RISC-V Processors (Thursday, June 1, 2023)
• RISE project gives RISC-V an open source software lift (Thursday, June 1, 2023)
• Semidynamics announces largest, fully customisable Vector Unit in the RISC-V market, delivering up to 2048b of computation per cycle for unprecedented data handling (Wednesday, May 31, 2023)
• UltraRISC Selects Valtrix STING for Verification of RISC-V SoC Designs (Wednesday, May 31, 2023)
• Industry Leaders Launch RISE to Accelerate the Development of Open Source Software for RISC-V (Tuesday, May 30, 2023)
• AndeSentry™ Collaborative Framework Enables Comprehensive RISC-V Security Solutions (Monday, May 29, 2023)
• MIPS Leverages Siemens' Veloce proFPGA platform to Implement and Make Available Capabilities of its New High-Performance eVocore P8700 RISC-V Multiprocessor (Monday, May 29, 2023)
• SiFive Gives WorldGuard to RISC-V International to Make this Robust Security Model More Accessible to the RISC-V Community (Tuesday, May 23, 2023)
• China's semiconductor developers eye shift to RISC-V architecture amid growing chip demand in cars, data centres and AI, executive says (Wednesday, May 17, 2023)
• Canonical enables Ubuntu on StarFive's VisionFive 2 RISC-V single board computer (Wednesday, May 10, 2023)
• Menta, Codasip join RISC-V 3D neuromorphic AI project (Monday, May 1, 2023)
• Esperanto Technologies Launches New Cloud Access Program to Broaden Access to its Massively Parallel, Low Power RISC-V Solutions (Wednesday, April 26, 2023)
• Andes Technology's N25F RISC-V Processor Enables Superior Performance And Low Power For Phison's X1 Enterprise SSD Controller (Monday, April 24, 2023)
• Esperanto Technologies Announces RISC-V Industry Milestone of Generative AI Models Running on ET-SoC-1; Access to be Made Available to the RISC-V Research Community (Tuesday, April 18, 2023)
• Semidynamics launches world's first fully customisable RISC-V IP cores (Sunday, April 16, 2023)
• Process agnostic fully customisable RISC-V IP cores (Sunday, April 16, 2023)
• Spanish startup performs RISC-V open core surgery (Sunday, April 16, 2023)
• Pine64 launches world's first RISC-V tablet device - PineTab-V for presale (Thursday, April 13, 2023)
• Chinese web giant Baidu backs RISC-V for the datacenter (Sunday, March 26, 2023)
• Is RISC-V Poised to Benefit From Arm's Licensing Changes? (Sunday, March 26, 2023)
• Andes Custom Extension™ (ACE) Supports AndesCore™ 45-Series Processors to Provide Flexible Acceleration (Wednesday, March 22, 2023)
• Ashling and Imagination announce Ashling's RiscFree™ C/C++ SDK support for RISC-V-based Catapult family (Tuesday, March 14, 2023)
• Codasip and IAR demonstrate dual-core lockstep for RISC-V (Monday, March 13, 2023)
• Imperas Collaborates with MIPS and Ashling to Accelerate RISC-V Application Software Development from SoC Concept to Deployment (Sunday, March 12, 2023)
• Imperas in RISC-V three way deal (Sunday, March 12, 2023)
• ARM adds custom instructions to M85 controller in RISC-V AI fightback (Sunday, March 12, 2023)