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RISC-V News

• Canonical enables Ubuntu on StarFive's VisionFive 2 RISC-V single board computer (Wednesday, May 10, 2023)
• Menta, Codasip join RISC-V 3D neuromorphic AI project (Monday, May 1, 2023)
• Esperanto Technologies Launches New Cloud Access Program to Broaden Access to its Massively Parallel, Low Power RISC-V Solutions (Wednesday, April 26, 2023)
• Andes Technology's N25F RISC-V Processor Enables Superior Performance And Low Power For Phison's X1 Enterprise SSD Controller (Monday, April 24, 2023)
• Esperanto Technologies Announces RISC-V Industry Milestone of Generative AI Models Running on ET-SoC-1; Access to be Made Available to the RISC-V Research Community (Tuesday, April 18, 2023)
• Spanish startup performs RISC-V open core surgery (Sunday, April 16, 2023)
• Process agnostic fully customisable RISC-V IP cores (Sunday, April 16, 2023)
• Semidynamics launches world's first fully customisable RISC-V IP cores (Sunday, April 16, 2023)
• Pine64 launches world's first RISC-V tablet device - PineTab-V for presale (Thursday, April 13, 2023)
• Is RISC-V Poised to Benefit From Arm's Licensing Changes? (Sunday, March 26, 2023)
• Chinese web giant Baidu backs RISC-V for the datacenter (Sunday, March 26, 2023)
• Andes Custom Extension™ (ACE) Supports AndesCore™ 45-Series Processors to Provide Flexible Acceleration (Wednesday, March 22, 2023)
• Ashling and Imagination announce Ashling's RiscFree™ C/C++ SDK support for RISC-V-based Catapult family (Tuesday, March 14, 2023)
• Codasip and IAR demonstrate dual-core lockstep for RISC-V (Monday, March 13, 2023)
• ARM adds custom instructions to M85 controller in RISC-V AI fightback (Sunday, March 12, 2023)
• Imperas in RISC-V three way deal (Sunday, March 12, 2023)
• Imperas Collaborates with MIPS and Ashling to Accelerate RISC-V Application Software Development from SoC Concept to Deployment (Sunday, March 12, 2023)
• Blueshift Memory to use Codasip custom compute to develop new memory-efficient processor technology (Wednesday, March 8, 2023)
• ProvenRun and SiFive deliver RISC-V-based secure Trusted Execution Environment (TEE) (Wednesday, March 8, 2023)
• Tiempo Secure announces TESIC RISC-V Secure Element IP and development kit (Tuesday, March 7, 2023)
• Andes Technology's N25F RISC-V Processor Enables Superior Immersive Scenarios for ASPEED Technology's Powerful Image Stitching SoC AST1230 (Monday, March 6, 2023)
• 2023 a Breakout Year for RISC-V (Sunday, March 5, 2023)
• DCD Presents RISC-V, Automotive & Cyber during Embedded World 2023 (Sunday, March 5, 2023)
• CAST Enhances RISC-V Processor Line for Low-Power and Functional Safety Applications (Thursday, March 2, 2023)
• 32bit RISC-V certified ISO 26262 ASIL-D ready by TÜV SGS (Monday, February 27, 2023)
• Arteris and SiFive Partner to Accelerate RISC-V SoC Design of Edge AI Applications (Monday, February 27, 2023)
• Imperas Collaborates with Synopsys on SystemVerilog based RISC-V Verification (Sunday, February 26, 2023)
• Ventana Micro Selects Imperas Solutions for RISC-V Processor Verification (Wednesday, February 22, 2023)
• embedded world 2023: Codasip presents on custom compute and RISC-V design (Wednesday, February 15, 2023)
• Andes And IAR Systems Together Enable Leading Vendor ILITEK To Accelerate The Development Of Its ISO 26262 Ready TDDI SoC ILI6600A (Tuesday, February 14, 2023)
• A closer look at security verification for RISC-V processors (Sunday, February 12, 2023)
• Andes Technology: Stepping into the 18th Year with Perseverance and Proud Accomplishments (Thursday, February 9, 2023)
• Could RISC-V become a force in high performance computing? (Tuesday, February 7, 2023)
• Could RISC-V become a force in high performance computing? (Tuesday, February 7, 2023)
• Intel Terminates RISC-V Development Project: What Happened? (Monday, January 30, 2023)
• NASA Recruits Microchip, SiFive, and RISC-V to Develop 12-Core Processor SoC for Autonomous Space Missions (Sunday, January 29, 2023)
• Intel kills its RISC-V Pathfinder development kit programme (Sunday, January 29, 2023)
• Nexperia invests in sustainable alternatives to batteries (Monday, January 23, 2023)
• Andes Technology Collaborates with LDRA to Deliver Integrated Tool Suite for Safety-Critical Software on Andes RISC-V CPU Solutions (Wednesday, January 18, 2023)
• Risc-V MCUs have 8 to 20 pins (Monday, January 16, 2023)
• Andes Unveils Details of its Entry Level D23 RISC-V Processor Core (Wednesday, January 11, 2023)
• Bluespec collaborates with Synopsys to address growing verification demands for RISC-V design community (Tuesday, January 10, 2023)
• Quad-core Risc-V development board with 3D GPU in Pico-ITX (Monday, January 9, 2023)
• RISC-V SBC VisionFive 2 Officially Shipped (Monday, January 9, 2023)
• MIPS Rolls Out Its First RISC-V Processor Core – It's a Big 'Un (Sunday, January 8, 2023)
• Ventana Introduces CES Audience to World's Highest Performance RISC-V CPU, Veyron V1 (Wednesday, January 4, 2023)
• SpacemiT makes important breakthroughs in RISC-V High-Performance Cores (Wednesday, January 4, 2023)
• €270m for RISC-V chiplets to build European exascale supercomputers (Wednesday, January 4, 2023)
• Google announces official Android RISC-V support (Tuesday, January 3, 2023)
• RISC-V chip to drive next generation app store of hearables (Monday, January 2, 2023)