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Wednesday, June 11, 2025

• I3C: The Next-Generation Serial Communication Bus
• Qualcomm opens new AI R&D center in Vietnam
• Honda Reportedly Plans Rapidus Investment to Secure Advanced Chips Beyond TSMC Deal
• UK plans $1bn AI supercomputer
• Synopsys Achieves PCIe 6.x Interoperability Milestone with Broadcom's PEX90000 Series Switch at PCI-SIG DevCon 2025
• Imec presents 150 GSa/s Digital-to-Analog Converter (DAC) achieving 300 Gb/s data transmission
• Cadence Advances Design and Engineering for Europe's Manufacturers on NVIDIA Industrial AI Cloud
• OPENEDGES Collaborates with Renesas on Memory Subsystem IPs for Next-Generation MPU Platform Development
• Synopsys Achieves PCIe 6.x Interoperability Milestone with Broadcom's PEX90000 Series Switch at PCI-SIG DevCon 2025
• Siemens' PAVE360 to support new Arm Zena Compute Subsystems
• VeriSilicon's AI-ISP Custom Chip Solution Enables Mass Production of Customer's Smartphones
• CFX's 130nm EEPROM IP Passes Customer Product-Level Evaluation, Ready for Mass Commercial Adoption
• Numem Addresses AI's Dirty Secret: Memory Is the Real Bottleneck
• IP Cores, Inc. ships new FFT4T Streaming Multi-Channel FFT Core
• Elliptic Labs' AI Platform Now Optimized for Ceva's NeuPro-Nano NPU - Enabling Smarter Edge Devices

Tuesday, June 10, 2025

• QuickLogic Joins Intel Foundry Chiplet Alliance
• TSMC May 2025 Revenue Report
• BOS Semiconductors, Selected for the 2025 Innovation Premier 1000
• IAR Platform Accelerates Embedded Development with Updated Toolchains for Arm and RISC-V
• Faraday Unveils FlashKit™-22RRAM: an eNVM-based SoC Development Platform for IoT
• Silicon Proven DisplayPort 1.4 Tx & Rx PHY IP Cores, Ready to license in 12/28/40/55nm
• sureCore launches comprehensive suite of silicon services
• Qualitas Semiconductor Successfully Develops UCIe v2.0-Compliant PHY IP, Enabling Up to 512Gbps Die-to-Die Connectivity
• IntoPIX Presents Its New Titanium Software Suite: Empowering AV-Over-IP Workflows With Speed, Quality & Interoperability
• VeriSilicon's Ultra-Low Energy NPU Provides Over 40 TOPS for On-Device LLM Inference in Mobile Applications
• Andes Technology Announces AndeSight™ IDE v5.4 to Streamline AI and Embedded Software Development on RISC-V

Monday, June 9, 2025

• How to Optimize Energy Consumption in IoT Devices
• Samsung's Gap with China's SMIC in Foundry Market Narrows to Mere 1.7%
• IntoPIX Accelerates Automotive Innovation With TicoRAW & JPEG XS On Lattice Low Power FPGAs
• VeriSilicon's Scalable High-Performance GPGPU-AI Computing IPs Empower Automotive and Edge Server AI Solutions
• Sarcina Technology advances photonic package design to address key data center challenges
• Qualcomm To Acquire UK's Alphawave For US$2.4 Billion

Sunday, June 8, 2025

• Andes Technology Unveils AndesAIRE™ AnDLA™ I370: A Next-Generation Deep Learning Accelerator for Edge and Endpoint AI

Friday, June 6, 2025

• Rambus at Rosenblatt's AI Summit: Navigating Memory in AI's Future
• FAMES Pilot Line Launches FAMES Academy To Train Europe's Chip Engineers with Skills to Leverage FD-SOI Technology and Design Circuits Using Advanced Setups
• €1.1bn plan for GF fab in Dresden – reports
• Project GENESIS minimizes ecological footprint in Europe's semiconductor industry
• Imec and Ghent University build integrated microwave photonics chip
• IntoPIX And Nextera-Adeas Announce Latest IPMX Demo Design With JPEG XS On Compact FPGAs At Infocomm 2025
• Keysight and Synopsys Deliver an AI-Powered RF Design Migration Flow for Transition from TSMC's N6RF+ to N4P Process Node

Thursday, June 5, 2025

• Transition Plan: Leonardo publishes its transition strategy
• NCSC proposes its PQC transition timeline to UK Policy makers: guiding the UK to a quantum-safe future, Jeremy Bradley NCSC
• Plug and Play Expands Semiconductor Ecosystem Program with New Synopsys Collaboration to Accelerate Chip Design Innovation
• TSMC Achieves 90% Yield in 2nm Memory Chip Production
• Intel Foundry Direct Connect 2025 Expands Roadmap And Partnerships
• Alphawave Semi Tapes Out Breakthrough 36G UCIe™ IP on TSMC 2nm, Unlocking Foundational AI Platform IP on Nanosheet Processes
• CAST Expands Functional Safety Line with Additional Certified IP Cores
• IntoPIX Showcases Smart Image Sensor Compression At AutoSens US 2025
• GlobalFoundries Announces $16B U.S. Investment to Reshore Essential Chip Manufacturing and Accelerate AI Growth
• Chips&Media Unveils WAVE-N: A Custom NPU for High-Quality, High-Resolution Imaging
• Automakers Can Launch AI-Defined Vehicles a Full Year Sooner - Powered by Arm Zena CSS

Wednesday, June 4, 2025

• Joseph von Fraunhofer Prize 2025 for research team at Fraunhofer IIS
• Cadence Extends Support for Automotive Solutions on Arm Zena Compute Subsystems
• Arm Unwraps Automotive Compute Platform Aimed at 'AI-Defined Vehicles'
• Using Design-to-Test Workflows and Managing the IP Lifecycle in Chiplet Designs
• New president reiterates commitment to Korea's tech future
• Dolphin Semiconductor Provides High-Efficiency DC-DC Converter in 40nm to XHSC for High-end Industrial Products Applications
• IP Cores, Inc. Announces New Shipment of PQC1 Hardware Accelerator for Post-Quantum Cryptography

Tuesday, June 3, 2025

• Siemens and Northrop Grumman continue collaboration to advance digital ecosystem
• Addressing e-waste with recyclable, healable circuit boards
• FlexGen Streamlines NoC Design as AI Demands Grow
• OpenGMSL™ Association Announces Formation to Revolutionize the Future of In-Vehicle Connectivity
• AccelerComm Secures $15m Funding to Speed Adoption of Technology for Space-Based 5G Networks to Deliver Universal Mobile Coverage

Monday, June 2, 2025

• Metanoia Communications Selects Andes Technology RISC-V Processor to Boost 5G O-RAN Efficiency and Accelerate Development
• Ex-TSMC executive joins Samsung Foundry to lead US expansion
• What's making smart cities and homes even smarter?
• Metanoia Communications Selects Andes Technology RISC-V Processor to Boost 5G O-RAN Efficiency and Accelerate Development
• Siemens and IBM collaborate to bring SysML v2 model-based systems engineering to Siemens Xcelerator
• 12-bit, 5MS/s SAR ADC IP Core for Ultra-Low Power Precision Applications: T2M Unveils New IP
• Chevin are proud to be awarded runner-up of Arm Silicon Startups Contest 2025
• HPC Innovator Taps Aion Silicon for $12M RISC-V Accelerator Program
• Making Technology Real: GlobalFoundries' Vision for the Future

Sunday, June 1, 2025

• Japan's Softbank will join hands with U.S. Intel to develop a new memory semiconductor that will be used for artificial intelligence (AI)

Friday, May 30, 2025

• How Cadence Is Powering Greener Semiconductor Innovation