Search News

Saturday, July 19, 2025

• NVIDIA's CUDA Now Supports RISC-V Processors in AI Systems, Marking a Major Development & Posing a Threat to the x86 and ARM Duopoly

Friday, July 18, 2025

• New Semiconductor Material for the Chips of the Future
• Korea joins Horizon Europe R&D programme
• TSMC to top $100bn as it plans 11 fabs in Taiwan
• President of Armenia Awards Synopsys Armenia President Yervant Zorian the First-Class Medal for "Service to the Homeland"
• Fraunhofer IPMS and DIVE target cleaner, more efficient chip production
• Cadence Races First to Release LPDDR6/5X Memory IP for AI Infrastructure
• Rapidus Achieves Significant Milestone at its State-of-the-Art Foundry with Prototyping of Leading-Edge 2nm GAA Transistors
• Europe's photonic computing opportunity: Q.ANT's funding boosts competitive edge
• Synopsys Completes Acquisition of Ansys

Thursday, July 17, 2025

• Fraunhofer develops "resource-efficient" measurement system for semiconductor wafer production
• German government plans new semiconductor factories
• European Funding Deals: SiPearl, Exein, Q.Ant Aim For Scaleup
• Sustainability in Action 2025, a strategic vision for a responsible and resilient business
• Quantropi brings post-quantum cryptography to STM32 just in time to face new threats
• TSMC Reports Second Quarter EPS of NT$15.36
• How Mature-Technology ASICs Can Give You the Edge
• The chiplet future could be harmonious
• Perceptia Devices Release pPLL08W, best-in-class RF PLL IP in GF22FDX
• Pioneering Performance: How Allegro DVT Is Accelerating AV1 Adoption in SiliconPermalink
• 2025 TSMC Technical Talk: Exploring Diverse Paths in Semiconductor Technology
• Innosilicon Scales LPDDR5X/5/4X/4 and DDR5/4 Combo IPs to 28nm and 22nm, Cementing Its Position as the "One Stop" for Memory Interface Solutions

Wednesday, July 16, 2025

• How AI is Pushing Semiconductor Manufacturing into a Generational Shift
• Semiconductor Fab Shakeups Signal Application-Focused Plans Ahead
• New architecture for AI datacentres proposed
• IHP, eMemory and its subsidiary PUFsecurity Break Ground on Open Access to Hardware PUF-based Security IP in Europe
• Thalia Design Automation launches AMALIA Platform 25.2
• ESD Alliance Reports Electronic System Design Industry Posts $5.1 Billion in Revenue in Q1 2025
• Siemens collaborates with SK keyfoundry to launch 130nm automotive power semiconductor Calibre PERC PDK
• InPsytech Tapes Out F2F SoIC Design Compliant with UCIE 2.0 Standard Enabling High-Speed Interconnects for 3D Heterogeneous Integration

Tuesday, July 15, 2025

• Niobium Superconducting Interconnects Open New Horizons for Quantum Computing
• Siemens' Veloce CS selected by Arm for Neoverse compute subsystems verification and validation
• GUC Tapes Out Industry-Leading UCIe Face-Up IP for TSMC SoIC-X
• Synopsys Receives All Necessary Approvals for Proposed Acquisition of Ansys

Monday, July 14, 2025

• Broadcom Cancels Spain Fab, Impacting Europe Semiconductor Ambitions
• HCLTech Q1 FY26: Reports 10.8% QoQ net profit decline at Rs. 3,843 Cr
• proteanTecs Launches Solution for System Production Analytics Based on Chip Telemetry
• IPrium releases SOQPSK-TG Demodulator for Aerospace Telemetry
• Breakthrough in AR/VR SoC Innovation: Full Suite of Cutting-Edge Interface & Analog IP Cores Licensed by Tier-1 U.S. Customer

Friday, July 11, 2025

• RISC-V Solidifies Presence in China as Global Momentum Builds
• IC'Alps Joins GlobalFoundries GlobalSolutions™ Ecosystem to Accelerate ASIC Development
• JEDEC Releases New LPDDR6 Standard to Enhance Mobile and AI Memory Performance
• IC'Alps Joins GlobalFoundries GlobalSolutions™ Ecosystem to Accelerate ASIC Development
• Arasan Announces immediate availability of its Total IP for Embedded USB2 (eUSB2) with Controller and PHY
• First Tetrivis LTD Consumer Product is Finalist in IEEE Smart Lighting "Let's Make Light" Contest.

Thursday, July 10, 2025

• TSMC June 2025 Revenue Report
• Europe's first HPC ARM processor lands at TSMC
• Andes Technology's AutoOpTune™ Applies Genetic Algorithms to Accelerate RISC-V Software Optimization
• Lossless Data Compression Webinar: Choosing Algorithms and IP Core Accelerators
• Andes Technology Advances High-Performance RISC-V Strategy with U.S.-based Design Center: Condor Computing

Wednesday, July 9, 2025

• Ceva, Inc. Schedules Second Quarter 2025 Earnings Release and Conference Call
• From smarter sensing to safer driving: GlobalFoundries solutions driving ADAS innovation
• Japanese Semiconductor Manufacturer Races Toward 2nm, Backed by IBM
• Exclusive: Arm estimates a 14-fold increase in data center customers since 2021, company says
• 3 Acquisitions Show Heavy Investment in AI, IoT, and High-End Processors
• SiPearl finally tapes out Europe's supercomputer chip
• Cadence Introduces Industry-First LPDDR6/5X 14.4Gbps Memory IP to Power Next-Generation AI Infrastructure
• Custom ASIC Design for CGM, TPMS & SATCOM applications from T2M-IP

Tuesday, July 8, 2025

• Samsung's Q2 profit falls short as chip slump, tariffs take toll
• Keysight and Korea Automotive Technology Institute Team Up to Improve Vehicle-to-Everything Component Testing
• OpenAI scales security to protect IP from Chinese foreign espionage threats
• French Startup Combines Electronics, Photonics And Optics For AI
• GlobalFoundries to Acquire MIPS to Accelerate AI and Compute Capabilities
• PUFsecurity, a subsidiary of eMemory, Achieves NIST CAVP Certification for PQC Algorithms, Launches PUFpqc Architecture for Quantum-Resilient SoCs

Monday, July 7, 2025

• 160-core RISC V Board Is The M.2 CoProcessor You Didn't Know You Needed
• Samsung Targets 70% 2nm Yield in 6 Months to Win Big Clients
• Menta Licenses Menta Embedded FPGA Programmable IP To Renesas For Its ForgeFPGA Product Line