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Friday, February 27, 2026

• TSMC Speeds up Expansion in Taiwan: up to 10 Fabs Reportedly under Construction or Starting in 2026
• Keysight to Demonstrate AI-Driven Wireless Innovations and 6G Readiness at Mobile World Congress 2026

Thursday, February 26, 2026

• Kaynes Semicon Pvt Ltd Adopts Advanced Simulation Solutions from Synopsys to Strengthen OSAT Capabilities
• ADTechnology Obtains ISO/IEC 27001:2022 Certification
• Keysight Technologies Reports First Quarter 2026 Results
• Embedded FPGA reaches a new stage of industrial maturity – Menta at Embedded World 2026
• Semidynamics Becomes 3-nm Ready, Moves Europe Toward Hardware Sovereignty
• SEALSQ Prioritizes Silicon-Based Quantum Computing to Align with Semiconductor Technology
• MIPI Alliance Releases UniPro v3.0 and M-PHY v6.0, Accelerating JEDEC UFS Performance for Edge AI in Mobile, PC and Automotive
• Accelerating semiconductor and electronic systems design using AI-powered digital twins
• Baya Systems and Aion Silicon Partner to Accelerate Next-Generation SoC and Chiplet Designs
• ADTechnology and Fraunhofer IIS Join Forces for Advanced ASIC and Chiplet Development
• Moon Photonics: moving towards large-scale quantum photonics
• Europe’s stealth leading-edge process technology
• GUC Announces Tape-out of UCIe 64G IP on TSMC N3P Technology

Wednesday, February 25, 2026

• China Reportedly Aims to Boost 7nm, 5nm Output Fivefold in Two Years, Driven by SMIC, Hua Hong
• UK-Based Arm to Train 15,000 Indonesian Engineers in Chip Design

Tuesday, February 24, 2026

• Cadence Completes Acquisition of Hexagon’s Design and Engineering Business, Advancing Leadership in Physical AI and Multiphysics
• MIPI Alliance Releases UniPro v3.0 and M-PHY v6.0, Accelerating JEDEC UFS Performance for Edge AI in Mobile, PC and Automotive
• Synopsys Appoints Former Deloitte Executive Peter Shimer to Board of Directors and Announces Board Transitions
• Baya Systems and Aion Silicon Partner to Accelerate Next-Generation SoC and Chiplet Designs
• Chips&Media Accelerates WAVE-N Ecosystem: Redefining the Future of Next-Generation Customized NPUs

Monday, February 23, 2026

• Fabless semiconductor startup Vervesemi raises $10 Mn in Series A round
• sensiBel Licenses Sofics’ Advanced ESD Solutions for their Studio-quality MEMS Microphone Technology
• RISC-V IP Core - TAE520 : R52, Comparable Performance functional-safety processor
• Renesas Develops SoC Technologies for Automotive Multi-Domain ECUs Essential for the SDV Era
• SEMIFIVE Partners with Niobium to Develop FHE Accelerator, Driving U.S. Market Expansion
• Siemens wins Best of Show Award for "Packaging: Design" at 2026 Chiplet Summit
• M31 Validates MIPI M-PHY v5.0 IP on 4nm, Advances 3nm Development to Enable UFS 4.1 Applications

Sunday, February 22, 2026

• Europractice 2.0 secures EU funding until September 2028
• Europe Doubles Down on Semiconductor Strengths
• Funding must be activated for semiconductor success
• Ceva to Participate in Upcoming Investor Conferences and Industry Events
• EnSilica to sponsor Tiny Tapeout workshop at the University of Sheffield

Thursday, February 19, 2026

• Chiplet Summit Announces 2026 Best of Show Award Winners
• India Budget 2026-2027: Semiconductors, Manufacturing, and Tax Reforms
• Former Altera CEO Sandra Rivera Assumes Role as VSORA’s Chair of the Board
• Cadence Reports Fourth Quarter and Fiscal Year 2025 Financial Results
• QuickLogic Announces $13 Million Contract Award for its Strategic Radiation Hardened Program
• CEA Demonstrates First Dynamically Routed Electro-Optical Router for Photonic Interposers
• Renesas Develops SoC Technologies for Automotive Multi-Domain ECUs Essential for the SDV Era
• STMicroelectronics Claims First Automotive MCU with Edge AI Acceleration
• Production-Ready, Full-Stack Edge AI Solutions Turn Microchip’s MCUs and MPUs Into Catalysts for Intelligent Real-Time Decision-Making
• Keysight Introduces PAM3 Signaling with New GDDR7 Transmitter Compliance Solution for Next-Generation Graphics Memory
• Keysight Unveils 3D Interconnect Designer for Chiplet and 3DIC Advanced Package Designs
• GlobalFoundries and Renesas Expand Partnership to Accelerate U.S. Semiconductor Manufacturing
• Samsung foundry steps up push to chase TSMC with 2 nm expansion and 1.4 nm plan
• TSMC scaling back 8‑inch production as advanced node demand surges

Wednesday, February 18, 2026

• Keysight Introduces PAM3 Signaling with New GDDR7 Transmitter Compliance Solution for Next-Generation Graphics Memory
• Keysight Unveils 3D Interconnect Designer for Chiplet and 3DIC Advanced Package Designs

Monday, February 16, 2026

• TES Launches its µEngine: Parallel CPU System for Deterministic Real-Time HDL Applications
• DVB-S2 Modulator Available For Implementation From Global IP Core
• Semiconductor sales set new record as logic and memory lead growth
• EnSilica to highlight turnkey ASIC expertise and European supply resilience at embedded world 2026
• Victor Peng Joins Rambus Board of Directors
• Fraunhofer IPMS develops new 10G TSN endpoint IP Core for deterministic high-speed Ethernet networks
• Aftermarket ADAS kit targets commercial vehicle retrofits
• BrainChip Announces Immediate Availability of Akida™ Pico for Remote Evaluation via FPGA Cloud
• RISC-V Pivots from Academia to Industrial Heavyweight
• SmartDV and Mirabilis Design Announce Strategic Collaboration for System-Level Modeling of SmartDV IP
• RISC-V IP Core Portfolio at Embedded World 2026, Powering Next-Gen Embedded Systems for Automotive, IoT & Industrial Systems…