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Thursday, May 29, 2025

• AI memory chip guru to unveil road map for next-generation HBMs
• Synopsys Issues Statement in Connection with BIS Letter
• TSMC to Open EU Design Center in Munich in Q3
• 300mm RF silicon interposer platform for chiplet-based heterogeneous integration demonstrates record-low insertion loss at frequencies up to 325GHz
• SCI Semiconductor raises £2.5m to develop security-enhanced microcontroller based on CHERI

Wednesday, May 28, 2025

• Keysight Technologies (KEYS) to Acquire Divested Assets from Synopsys and Ansys
• Trump Blocks Chip Design Software Firms From Selling In China
• Synopsys Posts Financial Results for Second Quarter Fiscal Year 2025
• CEA Backs RISC-V for Sovereign, Scalable Computing
• Arteris Bridges Hardware-Software Gap with New EDA Tool
• Rapidus to assist training in Vietnam's semiconductor industry
• Ireland Maps Out 'Silicon Island' National Semiconductor Strategy
• Toward High-Density Embedded LiDAR for the Autonomous Vehicle of Tomorrow
• ICTK Partners with BTQ of Canada for Quantum-safe Security Solutions
• SCI Semiconductor secures £2.5m towards developing CHERI-secured MCU
• TSMC dazzles in Amsterdam
• TSMC to Open First European Design Center in Munich by Q3 2025, Focusing on AI and Automotive
• EnSilica Establishes New Engineering Hub in Cambridge
• Brite Semiconductor Releases TCAM IP based on 28HKC+ Process

Tuesday, May 27, 2025

• Keysight Announces Executive Leadership Transitions and New Appointments
• Imec ITF World 2025: The hardware horizon for AI
• Alphawave IP extends Qualcomm PUSU deadline for third time
• Soitec reports fourth quarter revenue and Full-year results of fiscal year 2025
• Towards next-generation edge-AI technologies: EU consortium opens services to external customers
• Imec's 300mm RF silicon interposer platform for chiplet-based heterogeneous integration demonstrates record-low insertion loss at frequencies up to 325GHz

Monday, May 26, 2025

• Veriest & Xsight - Advancing Data Transfer for Cloud Data Centers
• CFX's 55nm BCD process OTP IP has been put on the shelves
• AMD sees TSMC as the clear favorite for 2nm, but Samsung remains in the game
• RISC-V Turns 15 With Fast Global Adoption
• High-Performance USB 3.2 Gen1 & Gen2 PHY and Controller IP Cores from T2M, Powers Next-Gen SoCs

Sunday, May 25, 2025

• Samsung to use Glass Substrate for Semiconductor manufacturing in 2028

Friday, May 23, 2025

• Smart Chips, Safe Trips: How DFT Powers the Future of Autonomy with Vijayaprabhuvel Rajavel
• Xiphera Wins ECSO STARtup Award 2025 for Innovation in Cybersecurity
• Analogue Insight and Tetrivis Announce Joint Development of "Eurytion RFK1," a UCIe based 12nm Ka/Ku-Band RF Chiplet Transceiver

Thursday, May 22, 2025

• How Taiwan stays ahead in semiconductor race
• Pioneering energy-efficient AI with innovative ferroelectric technology
• Samsung Electronics Nears Decision on Foundry Business Separation
• EnSilica expands satcoms user terminal portfolio with dual-beam, dual-polarization Ku-band analogue beamformer chipset
• SiFive Collaborates with Red Hat to Support Red Hat Enterprise Linux for RISC-V
• GlobalFoundries partners with A*STAR to accelerate advanced packaging innovation

Wednesday, May 21, 2025

• Siemens democratizes AI-driven PCB design for small and medium electronics teams
• Five workflows for tackling heterogeneous integration of chiplets for 2.5D/3D
• Intel eyes sale of network and edge unit as cost-cutting continues: report
• The RISC-V World Sees Changes, Milestones, and Innovations
• Creonic Adds oFEC Codec IP Core to Portfolio, Expanding High-Speed Networking Solutions for ASIC and FPGA
• Expedera's Origin Evolution NPU IP Brings Generative AI to Edge Devices
• Cost-Optimized PolarFire® Core FPGAs and SoCs from Microchip Technology Deliver High Performance with a 30% Lower Price Tag
• BrainChip CTO to Present on Architectural Innovation for Low-Power AI at the Embedded Vision Summit

Tuesday, May 20, 2025

• GlobalFoundries partners with A*STAR to accelerate advanced packaging innovation
• Steering the future: advanced satellite communications phased arrays with GF 45RFSOI, 45RFE and 130NSX
• Infineon to revolutionize power delivery architecture for future AI server racks with NVIDIA
• Movellus Claims First On-Die Power Delivery Network Analyzer
• Advanced IC Packaging: The Roadmap to 3D IC Semiconductor Scaling
• sureCore extends its sureFIT design service to include custom memory solutions for AI applications
• NVIDIA Unveils NVLink Fusion for Industry to Build Semi-Custom AI Infrastructure With NVIDIA Partner Ecosystem

Monday, May 19, 2025

• Six HCLTech campuses in India receive the coveted TRUE Zero Waste Platinum Certification
• Programmable AI Silicon Would Help Meet AI Workload Demand
• Siemens to bring advanced timing constraint capabilities to EDA design flow with Excellicon acquisition
• RISC-V Technology Seeing Growing Maturity and Penetration
• Secure-IC at Computex 2025: Enabling Trust in AI, Chiplets, and Quantum-Ready Systems
• InPsytech Joins Samsung SAFE™ IP Partner Program for Excellence in ONFI and UCIe IP Solutions
• Semidynamics: From RISC-V with AI to AI with RISC-V
• Codasip: Toward Custom, Safe, Secure RISC-V Compute Cores
• Versatile Whitebox 1G Ethernet PHY IP Core with BroadR-Reach™ for Connected Automotive and Industrial Systems

Sunday, May 18, 2025

• Imec and TNO Launch Holst Centre Photonics Lab to Accelerate Integrated Photonics Innovation in the Netherlands