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Thursday, May 1, 2025

• IBM Cloud is First Service Provider to Deploy Intel Gaudi 3
• Silvaco Partners with Kyung Hee University's Professor Jin Jang on AI-Powered Fab Technology Co-Optimization for Next Generation Display Technologies
• Ensuring IoT Designs Comply With the Cyber Resilience Act—and Are Seen to Do So
• Thalia enhances AMALIA Platform with new AI models to revolutionize analog, RF and mixed-signal IC design migration
• Intel Foundry Gathers Customers and Partners, Outlines Priorities
• Movellus Debuts Industry-First On-Die Power Delivery Network Analyzer
• Weebit Nano Q3 FY25 Quarterly Activities Report

Wednesday, April 30, 2025

• Enabling the next generation of smart glasses
• IC'Alps joins Intel Foundry Accelerator program as Value Chain Alliance (VCA) and Design Services Alliance (DSA) partner
• Intel tweaks its 18A process with variants tailored to mass-market chips, big AI brains
• Weebit Nano and DB HiTek to demonstrate chips integrating Weebit ReRAM at PCIM 2025
• EU likely to miss 2030 microchip target
• Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
• SkyeChip Joins Intel Foundry Accelerator IP Alliance
• Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
• Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
• Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
• Imec coordinates EU Chips Design Platform
• CFX 0.13μm eFuse OTP IP has been applied in the mass production of over 15,000 CMOS image sensors

Tuesday, April 29, 2025

• Award-winning, Nordic-powered outdoor asset tracker supports sustainable logistics
• Silvaco Expands Product Offerings in Photonics and Wafer-Scale Plasma Modeling for AI Applications with Acquisition of Tech-X Corporation
• Keysight EDA and Intel Foundry Collaborate on EMIB-T Silicon Bridge Technology for Next-Generation AI and Data Center Solutions
• Spain launches €800m quantum strategy
• QuickLogic to Report First Quarter Fiscal 2025 Financial Results on Tuesday, May 13
• Cadence to Buy Artisan to Support Chiplet, 3D IC Future
• European AI processor developer gets €40m for manufacturing
• VSORA Raises $46 Million to Bring World's Most Powerful AI Inference Chip to Market
• Codasip launches complete exploration platform to accelerate CHERI adoption
• BrainChip Collaborates with Chelpis-Mirle on Security Solution
• VeriSilicon Launches the Industry-Leading Automotive-Grade Intelligent Driving SoC Design Platform
• New Audio Sample Rate Converter (ASRC) IP Core from CAST Offers Versatility with High Fidelity
• UK grants 2D semiconductor research £6 million
• Thalia enhances AMALIA Platform with new AI models to revolutionize analog, RF and mixed-signal IC

Monday, April 28, 2025

• Premier ASIC and SoC Design Partner Rebrands as Aion Silicon
• Faraday Adds QuickLogic eFPGA to FlashKit-22RRAM SoC for IoT Edge
• NEXT Semiconductor Technologies Collaborates with BAE Systems to Develop Next Generation Space-Qualified Chips
• Wi-Fi 7 (802.11be) RF Transceiver IP Core Ready for High Speed Wireless Connectivity Applications
• Premier ASIC and SoC Design Partner Rebrands as Aion Silicon
• Baya Systems, Imagination Technologies and Andes Technology to Present on Heterogeneous Compute Architectures at Andes RISC-V CON Silicon Valley
• Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
• Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
• QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip

Friday, April 25, 2025

• Arteris Wins Two Gold and One Silver Stevie® Awards in the 2025 American Business Awards®
• Arteris Wins Two Gold and One Silver Stevie® Awards in the 2025 American Business Awards®
• Intel's CEO Lip-Bu Tan Reportedly Met With TSMC's CEO To Discuss Foundry Partnership; Raising Possibility of a Deal
• €6m for free space photonic networks for smart factories
• Aion Silicon to Showcase Advanced SoC Design Capabilities at Andes RISC-V CON Silicon Valley
• FPGA prototyping harnessed for RISC-V processor cores
• Faraday Adds QuickLogic eFPGA to FlashKit‑22RRAM SoC for IoT Edge
• Crypto Quantique announces QRoot Lite - a lightweight and configurable root-of-trust IP for resource-constrained IoT devices
• BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
• Xylon Introduces Xylon ISP Studio

Thursday, April 24, 2025

• Silicon Proven AV1 Decoder IP with support for 12-bit pixel size and 4:4:4 Chroma Sub-Sampling Released by Allegro DVT
• Cadence Enables Next-Gen AI and HPC Systems with Industry's Fastest HBM4 12.8Gbps IP Memory System Solution
• S2C and Andes Technology Announce FPGA-Based Prototyping Partnership to Accelerate Advanced RISC-V SoC Development
• PQShield launches UltraPQ-Suite for deeply specialized implementations of post-quantum cryptography
• BrainChip Extends RISC-V Reach with Andes Technology Integration
• M31 Collaborates with TSMC to Advance 2nm eUSB2 IP Innovation
• Andes Technology and Imagination Technologies Showcase Android 15 on High-Performance RISC-V Based Platform
• Synopsys and TSMC Usher In Angstrom-Scale Designs with Certified EDA Flows on Advanced TSMC A16 and N2P Processes
• TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
• Cadence and TSMC Advance AI and 3D-IC Chip Design with Certified Design Solutions for TSMC's A16 and N2P Process Technologies

Wednesday, April 23, 2025

• QuickLogic to Present and Exhibit at Andes RISC-V CON Technology Summit in San Jose
• Crypto Quantique publishes independent cetome analysis on streamlining CRA compliance with the QuarkLink security platform
• DVB-S2X Wideband LDPC/ BCH Encoder FEC IP Core Available For Licensing and Integration From Global IP Core
• Alphawave Semi Delivers Foundational AI Platform IP for Scale-Up and Scale-Out Networks
• Certus Semiconductor Joins TSMC IP Alliance Program to Enhance Custom I/O and ESD Solutions

Tuesday, April 22, 2025

• Andy Nightingale, VP of Product Marketing at Arteris – Interview Series
• MosChip® to showcase Silicon Engineering Services at TSMC 2025 North America Technology Symposium
• GlobalFoundries Accelerates GHG Reductions Commitments with Near Term Science-Based Target
• MosChip® to showcase Silicon Engineering Services at TSMC 2025 North America Technology Symposium
• Ceva Neural Processing Unit IP for Edge AI Selected by Nextchip for Next-Generation ADAS Solutions
• Thalia joins GlobalFoundries' GlobalSolutions Ecosystem to advance IP reuse and design migration
• Cadence Advances AI in the Cloud with Industry-First DDR5 12.8Gbps MRDIMM Gen2 Memory IP System Solution
• MosChip® to showcase Silicon Engineering Services at TSMC 2025 North America Technology Symposium

Monday, April 21, 2025

• BrainChip Gives the Edge to Search and Rescue Operations

Monday, April 21, 2025

• EU Bolsters Cybersecurity With NIS2 Directive
• EU Bolsters Cybersecurity With NIS2 Directive
• Analog Bits to Demonstrate IP Portfolio on TSMC 3nm and 2nm Processes at TSMC 2025 Technology Symposium 
• Shifting Sands in Silicon by Global Supply Chains
• Alphawave Semi Audited Results for the Year Ended 31 December 2024
• Analog Bits to Demonstrate IP Portfolio on TSMC 3nm and 2nm Processes at TSMC 2025 Technology Symposium Novel
• Equal1 advances scalable quantum computing with CMOS-compatible silicon spin qubit technology
• Analog Bits to Demonstrate IP Portfolio on TSMC 3nm and 2nm Processes at TSMC 2025 Technology Symposium
• Automating Hardware-Software Consistency in Complex SoCs

Saturday, April 19, 2025

• BOS Joins Plug and Play NeoCity 2025