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Monday, June 24, 2024

• True Circuits Introduces the JSPICEâ„¢ Design Environment (JDEâ„¢) at the Design Automation Conference

Monday, June 24, 2024

• EDA vendors put Intel EMIB interconnect in design flows for 3D ICs
• Siemens gets certification for Solido SPICE on Intel nodes, and adds EMIB
• Efabless Empowers 40 Commercial Companies to Design Chips
• Can Semiconductor Chips be Recycled?

Sunday, June 23, 2024

• SignatureIP Makes Network-on-Chip (NoC) Design Widely Accessible with Cloud-Based iNoCulatorâ„¢ Platform
• Baya Systems and Blue Cheetah Partner to Deliver Chiplet Interconnect Solutions
• Siemens delivers AI- accelerated verification for analog, mixed-signal, RF, memory, library IP and 3D IC designs in Solido Simulation Suite
• Semiwise, sureCore, and Cadence Showcase Breakthrough in Cryogenic CMOS Circuit Development for Quantum Computing and Energy-Efficient Data Centers
• Crypto Quantique, ZARIOT and Kigen unveil quantum-safe hardware root-of-trust for cellular IoT
• Ceva Extends its Smart Edge IP Leadership, Adding New TinyML Optimized NPUs for AIoT Devices to Enable Edge AI Everywhere
• Flex Logix Celebrates 10 Years of Success and Innovation
• T2M-IP Announces Silicon-Proven MIPI D-PHY v2.5 Tx and DSI-2 Tx Controller Low-Power, Cost-Effective IP Cores Solutions for Advanced SoCs
• Ventana CEO to Deliver a Keynote at RISC-V Summit Europe
• True Circuits Introduces the JSPICE™ Design Environment (JDE™) at the Design Automation Conference
• Figuring Out the Carbon Footprint of an Individual Chip
• RISC-V in Space Workshop in Gothenburg on April 2-3, 2025!

Thursday, June 20, 2024

• Tenstorrent Licenses Baya Systems' Fabric into next-generation AI and Compute Chiplet Solutions
• Baya Systems Introduces New Technology to Transform SoCs and Chiplets for Emerging Applications
• Andes Technology Showcases Leadership in AI and Automotive Applications at RISC-V Summit Europe 2024

Wednesday, June 19, 2024

• Dovetail Electric Aviation adopts Siemens Xcelerator to pioneer sustainable aviation
• Alphawave Semi Unlocks 1.2 TBps Connectivity for High-Performance Compute and AI Infrastructure with 9.2 Gbps HBM3E Subsystem
• lowRISC and Microsoft Collaborate to Help Bring the Revolutionary CHERIoT-Ibex Core to Production Grade
• Primemas Selects Achronix Embedded FPGA Technology For System-on-Chip (SoC) Hub Chiplet Platform
• System-level UCIe IP for early architecture analysis of 3D Chiplet Design and Packaging
• PQShield raises $37m in Series B funding to deliver the widespread commercial adoption of quantum resistant cryptography
• Breker Verification Systems Readies RISC-V CoreAssurance and SoCReady SystemVIP for Automated, Certification-level RISC-V Verification Coverage

Wednesday, June 19, 2024

• Movellus Introduces Aeonic Powerâ„¢ Product Family for On-Die Voltage Regulation

Tuesday, June 18, 2024

• onsemi selects Czech Republic for SiC production for advanced power semiconductors
• Slide Shows Samsung May be Developing a RISC-V CPU for In-memory AI Chip
• Intel 3 '3nm-class' process technology is in high-volume production
• Rapidus Set to Open 2-nm Pilot Fab, CEO Says
• EU proposes budget cuts to tech programmes in 2025
• Why do defects occur in battery production? Explainable AI supports process optimization.
• Global partnership unveils quantum-safe hardware root-of-trust for cellular IoT
• Alphawave Reveals Multiprotocol I/O Chiplet Tapeout, Collabs with Arm, Samsung
• YorChip announces Low Latency 200G Chiplet for edge AI
• M31 Announces the Launch of Advanced LPDDR Memory IP to Support HPC Applications
• Dream Chip and Cadence Demo Automotive SoC Featuring Tensilica AI IP at embedded world 2024
• Movellus Introduces Aeonic Power™ Product Family for On-Die Voltage Regulation
• OPENEDGES to Premiere PHY Vision 2.0 at Design Automation Conference 2024

Monday, June 17, 2024

• Are We Prepared for Cyberthreats in The New Era of Transportation?
• Samsung Foundry Struggles with Yield and Power Efficiency Issues
• Intel 3 Represents an Intel Foundry Milestone
• QuickLogic Joins Intel Foundry Accelerator IP and USMAG Alliance Programs
• Faraday to Exhibit Next-gen ASIC Solutions at DAC 2024
• Sequans Announces a New $15 Million Licensing Agreement

Sunday, June 16, 2024

• Imec unveils CMOS-based 56Gb/s zero-IF D-band beamforming transmitter, featuring superior output power and energy efficiency
• Initial members join CHERI Alliance to drive adoption of memory safety and scalable software compartmentalization
• EU is mandating Digital Product Passports

Friday, June 14, 2024

• Japan to send 200 engineers to U.S. for AI chip training at Tenstorrent
• Codasip Claims 'Best-in-Class' RISC-V Core for Power-Conscious Designs

Wednesday, June 12, 2024

• Cadence and Samsung Foundry Accelerate Chip Innovation for Advanced AI and 3D-IC Applications
• Axiomise Heads to RISC-V Summit Europe June 25-27 in Munich
• Flow Computing Emerges from Stealth with Licensable, On-Die Parallel Processing Enabling 100X Improved Performance For Any CPU Architecture
• Alphawave Semi Tapes Out Industry-First, Multi-Protocol I/O Connectivity Chiplet for High-Performance Compute and AI Infrastructure
• Consortium led by Crosshill Oy signs defense technology development agreement for F-35 Program with Lockheed Martin
• Samsung Showcases AI-Era Vision and Latest Foundry Technologies at SFF 2024
• Rapidus and IBM Expand Collaboration to Chiplet Packaging Technology
• Siemens collaborates with Samsung Foundry to expand 3D-IC enablement tools, optimize other EDA solutions for foundry's newest processes
• Sondrel secures major funding today
• ADTechnology announces next-generation platform "ADP600" at Samsung Foundry Forum 2024
• Synopsys Achieves Certification of its AI-driven Digital and Analog Flows and IP on Samsung Advanced SF2 GAA Process

Tuesday, June 11, 2024

• SEMIFIVE Collaborates with OPENEDGES on Chiplet Development
• Silvaco Announces Initiatives to Enhance Workforce Development in Semiconductor Industry
• SureCore Balances Power and Cooling Costs With Cryogenic Memory
• Alphawave Semi to Showcase Next-Generation PCIe® 7.0 IP Platform for High-Performance Connectivity and Compute at PCI-SIG® DevCon 2024
• Rambus Unveils PCIe 7.0 IP Portfolio for High-Performance Data Center and AI SoCs
• SEMIFIVE joins Arm Total Design with plans to develop Arm Neoverse-powered HPC Platform