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Tuesday, July 11, 2023

• Intelligent terminals applications given an innovation enhancement through AI acceleration
• Cadence Digital, Custom/Analog Design Flows Certified and Design IP Available for Intel 16 FinFET Process
• T2M Presents Silicon Proven MIPI D-PHY and DSI Controller IP Cores in 12FFC & 22ULL For Your Next Generation Display Products
• Crypto Quantique Selected for European Innovation Council (EIC) Grant Funding
• Cycuity Achieves ISO/SAE 21434 Certification for Automotive Cybersecurity Compliance

Monday, July 10, 2023

• Arasan's MIPI CSI-2 IP achieves ISO26262 ASIL-C Certification for MIPI C-PHY Connectivity
• Faraday's Launched SerDes Advanced Service to Accelerate ASICs into Production
• Spectral Design & Test Inc joins TSMC OIP IP Alliance
• Synopsys Delivers Certified EDA Flows and High-Quality IP for Intel 16 Process
• Siemens' Calibre platform now certified for IFS' Intel 16 process technology
• 'Correct by construction' tool for chip power layout down to 2nm
• Imperas details verification of automotive AI RISC-V vector processor IP
• Second contest for Generative AI chip design
• proteanTecs and Teradyne Partner to Bring Machine Learning-driven Telemetry to SoC Testing
• TSMC to construct second chip plant in Japan, aims to start production in 2026

Sunday, July 9, 2023

• TSMC June 2023 Revenue Report
• Siemens expand collaboration with AWS to help IC and electronics design customers accelerate innovation
• Siemens advances intelligent custom IC verification platform with new, AI-powered Solido Design Environment
• Electronic System Design Industry Logs $4 Billion in Revenue in Q1 2023, ESD Alliance Reports
• Cadence and Imperas Support NSITEXE in the Development of Advanced RISC V Vector Processor IP for Automotive AI Applications
• Siemens unveils Calibre DesignEnhancer for Calibre correct-by-construction IC layout optimization
• Alphawave Semi Spearheads Chiplet-Based Custom Silicon for Generative AI and Data Center Workloads with Successful 3nm Tapeouts of HBM3 and UCIe IP
• Xpeedic Launches High-Speed Digital Signal Integrity, Power Integrity Suite at Design Automation Conference
• End-to-end design and verification for PCIe 6.0
• Siemens advances intelligent custom IC verification platform with new, AI-powered Solido Design Environment
• Samsung Reports Net Zero Progress, Pledges Over $5B by 2030
• Bespoke EDA Differentiates Silicon Chips
• T2M invites Customers to explore High Performance, Cost-effective and Innovative IP Cores Solutions at DAC 2023

Thursday, July 6, 2023

• Efabless Corporation Launches Its Second AI-Generated Chip Design Contest
• sureCore and Universal Quantum announce tape out of cryogenic IP demonstrator chip
• Global Semiconductor Sales Increase 1.7% Month-to-Month in May

Wednesday, July 5, 2023

• Empowering Greener Future: Role Of Energy Storage Systems
• SilTerra Leverages Silvaco's Library Characterization and Optimization Tools to Boost Efficiency in the Development of its Foundry Standard Cell IPs
• Codasip welcomes Axel Strotbek as new chairman of the board
• Imperas Helps Navigate the Journey to RISC-V Based Silicon at DAC 2023
• UMC Reports Sales for June 2023
• Despite Export Ban on Equipment, China's Semiconductor Expansion in Mature Processes Remains Strong, Says TrendForce
• IC Manage GDP-XL Enterprise IP Catalog enables NXP to Improve IP Asset Management and Reuse
• True Circuits Attends 60th Design Automation Conference, Celebrates 25 Years of Timing Excellence
• New PNG Encoder IP Core Expands CAST's Lossless Compression Suite

Tuesday, July 4, 2023

• proteanTecs to Showcase the Future of Health and Performance Monitoring at DAC and SEMICON West 2023
• imec looks to process flow for sub-nm stacked CFET transistors
• Truechip: Exhibiting and Showcasing Latest Verification IPs and NOC IPs at Design Automation Conference (DAC) 2023
• GUC Monthly Sales Report - June 2023
• True Circuits Announces Availability of JSPICEâ„¢ Simulation and Design Environment
• Faraday to Exhibit FPGA-Go-ASIC, SONOS eFlash, and eFPGA Solutions at DAC 2023
• EUROPRACTICE starts offering access to Pragmatic's flexible integrated circuit foundry services through imec

Monday, July 3, 2023

• Infineon and Kontrol join forces to improve the safety of autonomous vehicles
• Advanced Packaging, Performance, power, size, weight, cost... The choice is yours!
• Samsung tapes out 2nm backside routing test chip
• Imec Advances GaN-on-Si and InP-on-Si Technologies for Next-Gen Wireless Communication
• AI Can't Design Chips Without People

Sunday, July 2, 2023

• Canada's semiconductor industry seeks renaissance from AI, shifting geopolitics
• Rapidus CEO Chasing Single-Wafer-Processing Dream
• Tiempo Secure's new TESIC RISC-V IP successfully passes SERMA CC EAL5+ security assessment tests
• AccelerComm Announces 5G PUSCH Channel Equalizer
• OPENEDGES Showcases Live Demo of PHY Vision at Design Automation Conference (DAC) 2023
• ADTechnology Joins Synopsys IP OEM Partner Program
• StarFive and Youyeetoo jointly delivered the official metal case for VisionFive 2
• Synopsys and Golden Electronics Collaborate to Expand Chip Design Talent in Jordan
• Single Carrier Modem Available For Immediate Licensing From Global IP Core
• Bluetooth Dual Mode V5.3 RF Transceiver IP Cores in 40nm ULP is Available for Immediate Licensing

Thursday, June 29, 2023

• CAST Introduces New MACsec Protocol Engine IP Cores