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Tuesday, June 27, 2023

• Leti details move to 10nm, 7nm FD-SOI process in Europe
• The European Project Creating Extensible, Energy-Efficient RISC-V CPUs
• CEVA Introduces Channel Sounding over Bluetooth® to Enable High-Accuracy Secure Positioning for Automotive, Industrial and the IoT Ecosystem
• Cadence Delivers Certified, Innovative Backside Implementation Flow to Support Samsung Foundry SF2 Technology
• Cadence Digital and Custom/Analog Design Flows Certified for Samsung Foundry's SF2 and SF3 Process Technologies
• Samsung Electronics Unveils Foundry Vision in the AI Era at Samsung Foundry Forum 2023
• Siemens extends support for Samsung Foundry's latest process technologies
• DCAN FD Full - a final step to CAN XL?
• Synopsys and Samsung Foundry Boost Power, Performance and Area for Modern SoCs on Samsung's SF2 Process
• Synopsys and Samsung Foundry Deepen Collaboration to Accelerate Multi-Die System Design for Advanced Samsung Processes
• CEVA Introduces Channel Sounding over Bluetooth to Enable High-Accuracy Secure Positioning for Automotive, Industrial and the IoT Ecosystem
• M31 Announces New 12nm Digital PLL IP to Drive the Benefits of IoT Clock Technology

Monday, June 26, 2023

• With NextGen, CEA is inventing the future generations of electronic chips to maintain France's competitiveness
• MAXEYE License and Deploy CEVA Sensor Fusion Software in Digital Pen for Leading Global Mobile OEM
• Bluespec Launches New MCUX RISC-V Processor That Enables Developers to Implement Custom Instructions and Add Accelerators
• Cadence AI-Based Virtuoso Studio Certified for Samsung Foundry PDKs for Mature and Advanced Nodes
• YorChip and Siloxit Collaborate on Industry's First Secure Data Acquisition Chiplet for Mass Markets
• MAXEYE License and Deploy CEVA Sensor Fusion Software in Digital Pen for Leading Global Mobile OEM
• Logic Fruit Technologies: Exhibiting and Showcasing Cutting-Edge Solutions at Design Automation Conference (DAC) 2023
• Comcores Unveils JESD204 IP Core Integration Guide to Streamline Customer PHY Integration Challenges
• Dolphin Design unveils an innovative IP for sound classification cutting down energy by 99%
• Blue Pearl Software and NanoXplore SAS team to Accelerate Development and Verification of Radiation Hardened FPGA Designs
• Arasan furthers the compliance of their I3C IP with its participation in the I3C Interop at MIPI Member Meeting
• Andes Technology Unveils the Annual Andes RISC-V CON, Scheduled for June 27th at the San Jose Airport DoubleTree Hotel

Sunday, June 25, 2023

• TSMC Plans Collaboration on 2nm Chips with Potential Clients
• CXL: The key to memory capacity in next-gen data centers
• How Will 5G Advanced Change RF Design?
• SEMIFIVE announces commercialization of its 5nm HPC SoC Platform with lead partner Rebellions, AI Chipmaker startup based in Korea
• Rapidus CEO Chasing Single-Wafer-Processing Dream
• 12Bit ADC and DAC IP Cores with High-Speed, High-Performance for Wireless applications that requires RF are available for immediate licensing
• DB GlobalChip Deploys Cadence's Spectre FX and AMS Designer, Accelerating IP Verification by 2X
• BrainChip Selects IPro Silicon IP to Serve Israel's high growth AI market

Saturday, June 24, 2023

• Leti Innovation Days: From Lab to Fab and the Future of Semiconductors

Thursday, June 22, 2023

• Synopsys: Blending AI Innovation With Robust IP For Semiconductor Dominance
• aiMotive achieves an industry first milestone with ISO26262 ASIL B certification for aiWare4 NPU IP

Wednesday, June 21, 2023

• Airbus and STMicroelectronics to develop silicon carbide power electronics for aircraft
• Do Startups Have a Place in the Semiconductor Supply Chain?
• Codasip partners with SmartDV to accelerate chip design projects
• Intel Provides Update on Internal Foundry Model
• DRAM Alternative Spawns U.K. Startup

Tuesday, June 20, 2023

• SiC and GaN Drive Vehicle Electrification
• OPENEDGES Achieves Tapeout of LPDDR5x/5/4x/4 PHY IP on 5nm SF5A Process Technology
• Quadric Announces Vision Transformer Support for Chimera GPNPUs

Monday, June 19, 2023

• MosChip appoints Dr. Naveed Ahmed Sherwani to the Board of Directors
• Concentrated competence in battery management: Vitesco Technologies France cooperates with CEA
• Jim Keller on AI, RISC-V, Tenstorrent's Move to Edge IP
• RISC-V Europe Summit Debuts Among Signs of Significant Growth in Advanced IoT Applications
• Global Top Ten IC Design Houses Break Even in Q1, Hope for Recovery in Q2 Bolstered by AI Demand, Says TrendForce
• Can Any Novel Architecture Topple the Mighty GPU?

Sunday, June 18, 2023

• Intel plans US$25 billion Israel wafer fab spend
• Samsung to apply AI, big data tech to entire chipmaking process
• Extending Moore's Law: CEA-Leti & Intel to Develop Atomically Thin 2D TMDs on 300mm Wafers Using Layer Transfer Technology for Future Transistor Scaling
• SEGGER adds Stack Overflow Prevention (STOP) technology to Embedded Studio for ARM
• Blueshift Memory and Crypta Labs to develop quantum-resilient cybersecurity memory module
• MosChip Announces the appointment of Semiconductor Industry Veteran Dr. Naveed Ahmed Sherwani to the Board of Directors
• Introducing T2M's Key IP Cores Empowering AI Chipsets and unleashing the true AI Potential
• Chips Acts' Role in Reshaping a Global Industry

Thursday, June 15, 2023

• Semiconductor Industry Sustainability Priorities - A Systems Engineering Opportunity
• Creonic Releases Ultrafast BCH Decoder IP Core, Processing One Codeword per Clock Cycle
• DFSPI IP Core from DCD supports all serial memories available on the market.
• M31 Has Expanded MIPI IP Portfolio, Successfully Validated 7nm MIPI C/D PHY Combo IP

Thursday, June 15, 2023

• Nanusens secures first IP license for its revolutionary MEMS-in-ASICsâ„¢ sensor technology