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Tuesday, June 21, 2022

• PCI-SIG® Announces PCI Express® 7.0 Specification to Reach 128 GT/s
• Foundry Output Value Up 8% in 1Q22
• RISC-V International emits more open CPU specs
• TSMC Creates Design Options for New 3nm Node
• Intento Design Secures Third Round of Investment to Accelerate Its Commercial Deployment
• MosChip Technologies Appoints Semiconductor Industry Veteran, DVR Murthy As "Vice President of Strategic Initiatives" to Implement and Execute Expanded Solution Offerings
• Codasip adds Veridify secure boot to RISC-V processors
• CEVA Extends its RivieraWaves UWB IP to Support CCC's Digital Key 3.0 Standard for Keyless Access to Vehicles
• M31 Technology has Developed and Validated the Ultra-Low Power 12nm PCIe 5.0 High-Speed Interface IP
• PCI-SIG Announces PCI Express 7.0 Specification to Reach 128 GT/s
• XtremeEDA to enable IoT security deployment with Crypto Quantique's solution using Codasip's RISC-V processor

Monday, June 20, 2022

• Dolphin Design wins an Embedded Award for Tiny Raptor, its Energy-Efficient Neural Network AI Accelerator
• Cadence Announces $100 Million Accelerated Share Repurchase Agreement
• Cadence Achieves PCIe 5.0 Specification Compliance for PHY and Controller IP in TSMC Advanced Technologies
• Expedera Expands Global Reach with New Regional Design Centers and Chinese Langauge Website
• Avery Design Systems PCI Express VIP Enables eTopus SerDes IP and Next-Generation ASIC and Chiplet applications to Achieve Compliance and High-Speed Connectivity
• SiFive Enhances Popular X280 Processor IP to Meet Accelerated Demand for Vector Processing
• Codasip Studio Mac extends potential to design for differentiation with RISC-V
• Codasip L31 customizable RISC-V core is an Embedded World Best in Show
• CV32E40P Core From OpenHW Group Sets the RISC-V Quality Standard For Open-Source Hardware IP
• RISC-V Announces First New Specifications of 2022, Adding to 16 Ratified in 2021
• OPENEDGES to Demonstrate Latest NPU IP, ENLIGHT at CVPR 2022
• Imagination launches IMG RTXM-2200 - its first real-time embedded RISC-V CPU
• OpenHW Group Announces RISC-V-based CORE-V MCU Development Kit for IoT Built with Open-Source Hardware & Software

Sunday, June 19, 2022

• Silicon Topology Joins TSMC Design Center Alliance (DCA)
• VisualSim Antenna System Designer enables simulation of Antenna and Communication Systems
• World's first end-to-end integration of ZKP with FPGAs.
• Fraunhofer IPMS develops CANsec Controller IP-Core CAN-SEC
• Huawei and Nordic cellular IoT licensing deal takes a big step towards industry-wide component-level licensing
• World's First AV1 Decoder Silicon IP with support for 12-bit pixel size and 4:4:4 Chroma Sub-Sampling Released by Allegro DVT
• Complete UFS 3.1 Controller solution (Analog / Digital IP Cores) licensed to China's leading Smartphone Company
• Samsung Ventures invests in Israeli AI systems and semiconductor company NeuReality

Thursday, June 16, 2022

• Embedded World fair: Menta will unveil an unprecedented collaboration with Everspin Technologies
• TSMC FINFLEX™, N2 Process Innovations Debut at 2022 North American Technology Symposium
• Cadence RFIC Solutions Support TSMC N6RF Design Reference Flow
• Synopsys Boosts 5G SoC Development Productivity with New RF Design Flow for TSMC N6RF Process

Wednesday, June 15, 2022

• Siemens extends support of multiple IC design solutions for TSMC's latest processes
• Avery Design Systems Announces Verification Support for New UCIe standard, Accelerating Adoption of Chiplet Interconnect Protocol
• QuickLogic and eTopus Announce Disaggregated, Flexible eFPGA Chiplet Template
• OpenFive Joins Universal Chiplet Interconnect Express (UCIe) Consortium
• Alchip Technologies Offers 3nm ASIC Design Services
• Renesas Develops Circuit Technologies for 22-nm Embedded STT-MRAM with Faster Read and Write Performance for MCUs in IoT Applications
• Cadence Design IP portfolio in TSMC's N5 Process Gains Broad Adoption Among Leading Semiconductor and System Companies
• CAST and Fraunhofer IPMS Mark 20-Year Partnership with Product of the Year Win
• SmartDV Charts Course Toward Chiplets, Joins Universal Chiplet Interconnect Express (UCIe)

Tuesday, June 14, 2022

• ST looks at joint European wafer fab with GlobalFoundries
• Renesas Launches Cellular-to-Cloud IoT Development Platforms Powered by RA and RX MCU Families
• Finwave targeting 5G with 3DGaN FinFET technology
• Japan targeting 2025-7 for 2nm process
• Think Silicon to Unveil Industry's First RISC-V 3D GPU at Embedded World 2022
• Veriest expands Embedded Software team to provide full engineering services
• The Five Biggest MCU Suppliers Accounted for 82% of 2021 Sales

Monday, June 13, 2022

• GaN Systems & TSMC Showcase Latest Power Electronics Advances at 2022 TSMC Technology Symposium
• Imagination GPU approved by HORIBA MIRA Certification Limited for functionally safe ADAS and HMI applications
• Allegro DVT Acquires Labwise Ltd. to Extend its Compliance Stream Business Line and Enrich its Products & Service Portfolio
• Real Intent Advances Meridian CDC with Multimode Coverage & Unprecedented 10X Efficiency
• Intrinsic ID Signs Representation Agreement with Kaviaz Technology to Extend the Commercial Reach of its Physical Unclonable Function (PUF) Security IP Solutions in Taiwan
• Renesas Announces Investment in Popular Open-Source Company Arduino to Access Huge Developer Community
• Codasip appoints Mike Eftimakis as VP of Strategy and Ecosystem
• intoPIX takes part in Major VSF Interoperability Demonstrations at VidTrans 2022

Sunday, June 12, 2022

• BrainChip, Edge Impulse Team to Develop Low-Cost Embedded ML Systems
• Global Fab Equipment Spending Expected to Reach Record $109 Billion in 2022, SEMI Reports
• Cadence Extends Cloud Leadership with Transformational Cadence OnCloud SaaS and e-Commerce Platform
• Altair Expands Electronic System Design Technology with Acquisition of Concept Engineering
• IAR Systems accelerates innovation for solutions based on Arm Cortex-M85 processor
• Synopsys Drives Chip Innovation for Next-Generation Mobile and HPC Designs on TSMC N3E and N4P Processes
• Cadence Digital and Custom/Analog Design Flows Certified by TSMC for Latest N3E and N4P Processes
• SkyWater Announces Availability of SRAM Memory Compiler for 90 nm Strategic Rad Hard by Process Offering
• Wi-Fi 6 (AX)/BLE/15.4 22nm Combo RF IP Core, Licensed to a leading Chinese Semiconductor Company for IoT Chipset
• Alphawave IP Announces Availability of Two New Interconnect IP Products in TSMC Advanced Processes
• Analog Bits to Demonstrate Pinless PLL and Sensor IP's in TSMC N5 Process at TSMC 2022 North America Technology Symposium
• TSMC May 2022 Revenue Report

Thursday, June 9, 2022

• SkyWater adds FDSOI SRAM IP
• Mosaid Announces Semiconductor Process License Agreement
• Cadence Cerebrus AI-Based Solution Delivers Transformative Results on Next-Generation Customer Designs
• Mosaid Acquires Major Semiconductor Process Portfolio
• Mark Potter and Christian Klingler Join proteanTecs Advisory Board
• CAES announces Space Grade Qualification of Quad Core LEON4FT Microprocessor